基于FPGA的可重构多总线通信单元设计

发布时间：2018-08-01 08:55

【摘要】：随着科学技术的发展，现代测试系统正向着“一机多用、一机多型”的软硬件一体化方向发展，因此，要求试验与测试一体化平台的设计具有标准化、通用化、可扩展化等特点。在试验与测试一体化平台中，外部总线是重要的组成部分之一。本文以试验与测试一体化平台的总线技术要求为背景，采用基于FPGA的可重构技术，以多种串行总线为应用条件，开展了基于FPGA的多总线通信单元设计。论文使用现场可编辑逻辑门阵列（FPGA）芯片为主控芯片，利用其“硬件设计软件化”的优点，以可编程形式最大程度的满足系统设计各个要求。论文从研究背景入手，在分析相关技术的国内外研究现状基础上，依据其主要功能，提出了系统的总体设计方案。根据设计方案，首先对系统硬件进行了设计，，包括FPGA硬件单元里的时钟电路、电源电路、配置电路、复位电路和外部存储电路以及总线单元里CAN总线、USB总线、RS-422的电路等；接着，通过分析各种串行总线的协议规范，使用硬件描述语言并结合SJA1000、CY7C68013A、MAX3160协议芯片完成了总线的FPGA设计；系统根据FPGA可以多次重复配置的特点，采用可重构技术动态地改变系统上FPGA芯片内部逻辑功能，通过上位机LabView多总线通信单元来选调配置文件，从而动态的改变了系统的整体功能，并对可重构配置进行了时序仿真；最后，通过实验对整个系统进行了验证，其功能达到预期目标。采用FPGA可重构技术对各种总线进行动态配置，是可重构技术在总线解决通用化、集成化、微型化等技术问题的实际应用。本设计实现了与各种通用、专用试验与测试设备信息共享的目标，提高了信息传递的高效性、快速性和可靠性。
[Abstract]:With the development of science and technology, modern test system is developing towards the integration of hardware and software of "one machine, one machine". Therefore, the design of test and test integration platform is required to be standardized and universal. Extensible and other characteristics. The external bus is one of the most important parts in the integrated test and test platform. In this paper, the design of multi-bus communication unit based on FPGA is carried out under the background of the bus technology requirement of the test and test integration platform, the reconfigurable technology based on FPGA and the application condition of multiple serial buses. In this paper, the field editable logic gate array (FPGA) chip is used as the main control chip, and the advantages of "hardware design software" are used to meet the requirements of the system design in the most programmable form. On the basis of analyzing the current research situation of related technologies at home and abroad and according to their main functions, this paper puts forward the overall design scheme of the system from the point of view of the research background. According to the design scheme, the system hardware is designed firstly, including clock circuit, power circuit, configuration circuit, reset circuit and external memory circuit in FPGA hardware unit, and CAN bus RS-422 circuit in bus unit, etc. By analyzing various protocol specifications of serial bus, using hardware description language and combining with SJA1000 CY7C68013AHMAX3160 protocol chip, the FPGA design of the bus is completed, and the system can be configured repeatedly according to the characteristics of FPGA. The internal logic function of FPGA chip is changed dynamically by using reconfigurable technology, and the configuration file is selected by LabView multi-bus communication unit of host computer, which dynamically changes the whole function of the system, and the timing simulation of reconfigurable configuration is carried out. Finally, the whole system is verified by experiment, and its function reaches the expected goal. Using FPGA reconfigurable technology to dynamically configure all kinds of buses is the practical application of reconfigurable technology in solving the technical problems of generalization integration miniaturization and so on. The design achieves the goal of information sharing with all kinds of universal, special test and test equipment, and improves the efficiency, rapidity and reliability of information transmission.
【学位授予单位】：中北大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN791

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