嵌入式处理器中多媒体加速单元的研究

发布时间：2018-08-02 21:17

【摘要】：在嵌入式移动设备中应用多媒体技术,需要同时考虑性能、成本、功耗以及灵活性等诸多方面的因素,带有媒体扩展单元的嵌入式处理器作为其中一种较为平衡的解决方案,得到了广泛的关注与研究。本论文以此为背景,在研究多种媒体运算以及典型扩展指令集的基础上,对嵌入式处理器中的媒体加速单元进行设计并实现一种新型去隔行算法,现将本论文的主要研究工作与创新点归纳如下： 1.对多种媒体运算与扩展指令集的研究。论文针对多媒体应用中两大重要的技术——音视频编解码和后处理技术进行展开,分别对MPEG2、MPEG4、H.264和图像缩放、视频去隔行、帧频提升进行算法研究、运算提取以及实验分析,同时借鉴主流的多媒体扩展指令集,结合现有处理器和指令集的特点,根据Amdah1定律等影响处理器性能的因素,对媒体扩展指令集进行设计,本文重点对SIMD加减、乘法及其相关的SAD、乘累加指令进行研究。 2.多媒体加速单元的设计。在综合考虑已有处理器机制的基础上,多媒体加速单元整体采用乱序执行和流水线平衡划分的策略。通过采用成熟的乘法器IP,提升了设计的可靠性；通过将高位宽乘法运算分解为并行的低位宽乘法运算,缩短了组合逻辑的延时；通过内部的重排序机制,保证了精确的中断和异常处理；通过门控时钟和操作数隔离的技术,有效控制了功耗。 3.去隔行的多媒体应用研究。本文提出了一种新型的基于运动分类的自适应去隔行算法,创新性地引入了运动等级分类、维纳中值滤波以及三重中值滤波,仿真实验表明,算法具有一定的先进性。同时,采用媒体处理器加以实现,将其中复杂的运算与媒体指令集进行映射,并将其处理结果与算法仿真结果进行对比分析。
[Abstract]:The application of multimedia technology in embedded mobile devices requires consideration of performance, cost, power consumption, flexibility and many other factors. Embedded processors with media expansion units are considered as one of the more balanced solutions. It has received extensive attention and research. Based on the research of various media operations and typical extended instruction sets, this paper designs the media acceleration unit in embedded processor and implements a new de-interlacing algorithm. The main research work and innovation of this paper are summarized as follows: 1. Research on multiple media operations and extended instruction sets. In this paper, two important technologies in multimedia applications, audio and video coding, decoding and post-processing, are developed. The algorithms, arithmetic extraction and experimental analysis of MPEG2 / MPEG4 / H.264 and image scaling, video de-interlacing, frame rate promotion are studied, respectively. At the same time, referring to the mainstream multimedia extended instruction set, combining the characteristics of the existing processor and instruction set, according to the factors that affect the processor performance, such as Amdah1's law, the media extended instruction set is designed. The emphasis of this paper is on the addition and subtraction of SIMD. Multiplication and related SAD, multiplicative cumulative instruction to study. 2. The design of multimedia acceleration unit. On the basis of synthetically considering the existing processor mechanism, the multimedia accelerating unit adopts the strategy of disorderly execution and pipeline balanced partitioning. By using mature multiplier IPs, the reliability of the design is improved. By decomposing the high bit width multiplication into parallel low width multiplication, the delay of combinational logic is shortened, and the internal reordering mechanism is used. Accurate interrupt and exception handling are ensured, and the power consumption is effectively controlled by the gated clock and Operand isolation technology. Research on Deinterlaced Multimedia applications. In this paper, a new adaptive de-interlacing algorithm based on motion classification is proposed, which innovatively introduces motion classification, Wiener median filter and triple median filter. The simulation results show that the algorithm is advanced to some extent. At the same time, the complex operation is mapped to the media instruction set by the media processor, and the processing results are compared with the simulation results of the algorithm.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP368.1;TP332

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