低功耗音频DSP并行编程环境设计与实现
发布时间：2018-08-11 17:03
【摘要】：近年来，智能音频应用的普及对手持设备的计算能力的要求越来越高，然而手持设备的续航时间却越来越短。更高的性能，更低的功耗，是移动处理器的主要发展方向。多核凭借其强大的处理能力与相对较为合理的功耗、散热、制造成本成为了移动处理器的主流方案。 APC（Audio Processing Core）是面向音频应用优化设计的低功耗DSP，采用多核设计，具有计算资源受限、多级混合型存储架构以及无操作系统环境等特点。 音频应用必须经过并行化才能发挥多核APC的计算能力。并行程序需要通过并行编程模型来编写。现有的并行编程模型各自适合特定架构。APC也需要一套对其硬件架构优化的并行程模型。 本文为多核APC设计并实现了一套并行编程模型。该并行编程模型具有轻量级的运行时环境，支持多级混合型存储架构，支持多种核间交互方式。 为了评估文中并行编程模型的性能以及开销，设计并实现了一个APC多核指令集模拟器，模拟并行程序运行所需的硬件环境。 将四个实验用例移植到多核指令集模拟器上，实验结果表明，，文中的并行编程环境以较小的开销、简洁易用的编程接口发挥出了多核APC的计算能力。该并行环境的设计实现过程，对面向特定应用的低功耗DSP的并行编程环境设计具有一定的参考意义。
[Abstract]:In recent years, the popularity of intelligent audio applications requires more and more computing power of handheld devices, but the lifetime of handheld devices is becoming shorter and shorter. Higher performance and lower power consumption are the main development directions of mobile processors. With its powerful processing power and relatively reasonable power consumption, heat dissipation and manufacturing cost, multicore has become the mainstream solution of mobile processor,. APC (Audio Processing Core) is a low-power DSPs for the optimization design of audio applications, and adopts multi-core design. It has the characteristics of limited computing resources, multilevel hybrid storage architecture and no operating system environment. Audio applications must be parallelized to achieve multi-core APC computing power. Parallel programs need to be written in parallel programming models. The existing parallel programming models are suitable for specific architectures. APC also needs a set of parallel stroke models to optimize its hardware architecture. This paper designs and implements a parallel programming model for multi-core APC. The parallel programming model has a lightweight runtime environment, supports a multi-level hybrid storage architecture, and supports a variety of intercore interactions. In order to evaluate the performance and overhead of the parallel programming model in this paper, a APC multi-core instruction set simulator is designed and implemented to simulate the hardware environment required for parallel program running. Four experiment cases are transplanted to the multi-core instruction set simulator. The experimental results show that the parallel programming environment in this paper exerts the computing power of multi-core APC with small overhead and simple and easy-to-use programming interface. The design and implementation process of this parallel environment has certain reference significance for the design of low power DSP parallel programming environment for specific applications.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TP311.11
本文编号：2177657
[Abstract]:In recent years, the popularity of intelligent audio applications requires more and more computing power of handheld devices, but the lifetime of handheld devices is becoming shorter and shorter. Higher performance and lower power consumption are the main development directions of mobile processors. With its powerful processing power and relatively reasonable power consumption, heat dissipation and manufacturing cost, multicore has become the mainstream solution of mobile processor,. APC (Audio Processing Core) is a low-power DSPs for the optimization design of audio applications, and adopts multi-core design. It has the characteristics of limited computing resources, multilevel hybrid storage architecture and no operating system environment. Audio applications must be parallelized to achieve multi-core APC computing power. Parallel programs need to be written in parallel programming models. The existing parallel programming models are suitable for specific architectures. APC also needs a set of parallel stroke models to optimize its hardware architecture. This paper designs and implements a parallel programming model for multi-core APC. The parallel programming model has a lightweight runtime environment, supports a multi-level hybrid storage architecture, and supports a variety of intercore interactions. In order to evaluate the performance and overhead of the parallel programming model in this paper, a APC multi-core instruction set simulator is designed and implemented to simulate the hardware environment required for parallel program running. Four experiment cases are transplanted to the multi-core instruction set simulator. The experimental results show that the parallel programming environment in this paper exerts the computing power of multi-core APC with small overhead and simple and easy-to-use programming interface. The design and implementation process of this parallel environment has certain reference significance for the design of low power DSP parallel programming environment for specific applications.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TP311.11
【参考文献】
相关期刊论文 前3条
1 王昌林;张勇;李东生;;CMOS集成电路功耗分析及其优化方法[J];舰船电子工程;2006年03期
2 陶峰峰,付宇卓;DSP指令集仿真器的设计与实现[J];计算机仿真;2005年09期
3 李晋,葛敬国;Linux下互斥机制及其分析[J];计算机应用研究;2005年08期
本文编号：2177657
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2177657.html
