DSP数据缓存的设计与验证

发布时间：2018-08-15 17:45

【摘要】：随着多媒体移动通信的应用需求越来越大，对嵌入式处理器操作系统支持、协议控制和数据运算能力的要求越来越高。因此，融合MCU与DSP特性的嵌入式DSP成为一个重要研究方向，其数据缓存的设计也具有重要意义。本文根据融合架构的ZW100DSP设计了基于可配置的Cache与便笺存储器(SPR)的数据缓存架构。本文首先对缓存基本原理进行了分析，以性能功耗比为指标评价各种优化Cache的策略，确定数据缓存的基本参数。该数据缓存模块以两路组相联、最近最少使用替换算法(LRU)为基础结构，并使用虚拟地址进行索引，物理地址判断是否命中以及同时对Cache存储体和Tag存储体进行访问的方法来加快访问速度；为了更好的维护存储一致性，加入了Cache管理指令，，来满足开发人员对Cache进行控制的需求；针对ZW100数据缓存可配置的特性设计了特殊寄存器模块来实现对不同大小缓存的支持；为了减少缺失代价，数据缓存控制模块中加入了LineBuffer，可及时向DSP返回所访问的关键双字，并且为了加快没有主Cache存在时的访存效率，为该Line Buffer加入了Nano-Cache模式；为了加快上下文切换速度，设计了128位的上下文切换接口，扩展了上下文切换区域(CSA)位于SPR时上下文切换的带宽，并且加入了上下文操作模块来处理CSA不位于SPR时的情况；另外，设计了高速片上总线接口，使该模块方便的与其他模块进行互联；并在数据通路中进行了优化，满足DSP和其他总线Master对SPR的访问需求而不发生冲突；最后使用基于事务的定向验证方法对该模块进行了验证，提高了验证效率，验证结果表明该数据缓存模块完全实现了设计规范中所要求的功能。
[Abstract]:With the increasing application demand of multimedia mobile communication, the requirement of embedded processor operating system support, protocol control and data operation ability is becoming higher and higher. Therefore, embedded DSP with MCU and DSP features has become an important research direction, and the design of data cache is also of great significance. In this paper, a data cache architecture based on configurable Cache and note memory (SPR) is designed according to the fusion architecture of ZW100DSP. In this paper, the basic principle of cache is analyzed, and the performance / power ratio is used as the index to evaluate the strategies of optimizing Cache and determine the basic parameters of data cache. The data cache module is associated with two groups, and the most recent use of the replacement algorithm (LRU) as the infrastructure, and use virtual addresses for indexing, The physical address determines whether the hit is hit or not, as well as the method of accessing both the Cache and Tag repositories to speed up the access speed. In order to maintain storage consistency better, Cache management instructions are added. To meet the needs of developers to control the Cache; to design special register modules to support different sizes of cache for the configurable features of ZW100 data cache; to reduce the cost of missing, The LineBuffer is added to the data cache control module, which can return the key word to the DSP in time, and in order to speed up the memory access efficiency in the absence of the main Cache, the Nano-Cache mode is added to the Line Buffer, and the speed of context switching is accelerated. A 128-bit context switching interface is designed, which extends the bandwidth of context switching when the context switching region (CSA) is located in the SPR, and adds a context operation module to handle the case where the CSA is not located in the SPR. A high-speed on-chip bus interface is designed to make the module easily interconnect with other modules, and the data path is optimized to meet the SPR access requirements of DSP and other bus Master without conflict. Finally, the transaction-based directional verification method is used to verify the module, which improves the efficiency of the verification. The verification results show that the data cache module fully implements the functions required in the design specification.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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