纳米硅非挥发性存储器的工艺处理和存储特性研究
发布时间：2018-08-21 12:49
【摘要】：随着半导体集成电路的不断发展,传统的Flash存储器的发展遭遇了瓶颈。基于纳米晶粒的浮栅存储器由于其分立电荷存储的优点受到越来越多的关注,而基于不同机制的新型阻变存储器由于其高速的读写速度及其与当前CMOS相兼容的制备工艺近年来成为存储器领域的研究热点,如何利用现代的半导体工艺来提高这些存储器的性能是目前科学界和产业界的重要研究课题。 本文针对一种纳米硅浮栅存储器结构——poly-Si/Si3N4/nc-Si/SiO2MOS结构,研究了以Al电极为掩膜反应离子刻蚀(RIE)多晶硅的工艺技术,获得了比较理想的刻蚀工艺条件,成功制备了独立的poly-Si/Si3N4/nc-Si/SiO2MOS单元。为了改进阻变纳米硅存储器的电学特性,我们采用纳米球RIE工艺制备了纳米硅阵列,在阻变纳米硅存储器中实现了对硅量子点的空间分布的限制。在此基础上我们进一步利用高精度的光刻工艺来减小阻变纳米硅存储器顶电极面积以实现纳米硅存储器中电场分布的限制,以此优化其阻变性能,发现随着电极面积减小阻变纳米硅存储器的性能获得了提高。 在成功获得独立poly-Si/Si3N4/nc-Si/SiO2MOS结构单元的基础上,对其电容、电导特性进行了测量,通过C-V曲线计算了nc-Si的密度,研究了纳米硅在电荷存储中所起的主要作用。发现了C-V曲线随着频率的增加沿着电压的负方向偏移,并观察到了G/ω-V曲线中电导峰随频率升高而偏移,基于对变频C-V曲线和G/ω-V曲线随随频率变化关系的详细分析,证明了纳米硅和界面态在电荷存储中的共同作用。
[Abstract]:With the continuous development of semiconductor integrated circuits, the development of traditional Flash memory has encountered a bottleneck. Floating gate memory based on nanocrystalline has attracted more and more attention because of its advantages of discrete charge storage. In recent years, novel resistive memory based on different mechanisms has become a research hotspot in the field of memory due to its high speed of reading and writing and its compatibility with current CMOS. How to use modern semiconductor technology to improve the performance of these memories is an important research topic in science and industry. In this paper, a poly-Si / Si _ 3N _ 4 / nc-Si / Si _ 2O _ 2MOS structure is studied. The etching process of (RIE) polysilicon with Al electrode as the mask ion is studied. The ideal etching conditions are obtained, and the independent poly-Si/Si3N4/nc-Si/SiO2MOS cells are successfully fabricated. In order to improve the electrical properties of the resistive nanocrystalline silicon memory, a nanospheres RIE process was used to fabricate the nanocrystalline silicon arrays, which limited the spatial distribution of the silicon quantum dots in the resistive nanocrystalline silicon memory. On this basis, we further use high-precision lithography to reduce the area of the top electrode of the resistive nanocrystalline silicon memory so as to limit the electric field distribution in the nano-silicon memory and optimize its resistance performance. It is found that with the decrease of electrode area, the performance of nano silicon memory is improved. On the basis of successfully obtaining the independent poly-Si/Si3N4/nc-Si/SiO2MOS structure unit, the capacitance and conductance characteristics are measured, the density of nc-Si is calculated by C-V curve, and the main role of nano-silicon in charge storage is studied. It is found that the C-V curve shifts along the negative direction of the voltage with the increase of frequency, and the conductivity peak in the G / 蠅 -V curve is offset with the increase of the frequency. Based on the detailed analysis of the relationship between the frequency variation of the frequency conversion C-V curve and the G / 蠅 -V curve, The interaction of nano-silicon and interfacial states in charge storage is proved.
【学位授予单位】：南京大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
本文编号：2195786
[Abstract]:With the continuous development of semiconductor integrated circuits, the development of traditional Flash memory has encountered a bottleneck. Floating gate memory based on nanocrystalline has attracted more and more attention because of its advantages of discrete charge storage. In recent years, novel resistive memory based on different mechanisms has become a research hotspot in the field of memory due to its high speed of reading and writing and its compatibility with current CMOS. How to use modern semiconductor technology to improve the performance of these memories is an important research topic in science and industry. In this paper, a poly-Si / Si _ 3N _ 4 / nc-Si / Si _ 2O _ 2MOS structure is studied. The etching process of (RIE) polysilicon with Al electrode as the mask ion is studied. The ideal etching conditions are obtained, and the independent poly-Si/Si3N4/nc-Si/SiO2MOS cells are successfully fabricated. In order to improve the electrical properties of the resistive nanocrystalline silicon memory, a nanospheres RIE process was used to fabricate the nanocrystalline silicon arrays, which limited the spatial distribution of the silicon quantum dots in the resistive nanocrystalline silicon memory. On this basis, we further use high-precision lithography to reduce the area of the top electrode of the resistive nanocrystalline silicon memory so as to limit the electric field distribution in the nano-silicon memory and optimize its resistance performance. It is found that with the decrease of electrode area, the performance of nano silicon memory is improved. On the basis of successfully obtaining the independent poly-Si/Si3N4/nc-Si/SiO2MOS structure unit, the capacitance and conductance characteristics are measured, the density of nc-Si is calculated by C-V curve, and the main role of nano-silicon in charge storage is studied. It is found that the C-V curve shifts along the negative direction of the voltage with the increase of frequency, and the conductivity peak in the G / 蠅 -V curve is offset with the increase of the frequency. Based on the detailed analysis of the relationship between the frequency variation of the frequency conversion C-V curve and the G / 蠅 -V curve, The interaction of nano-silicon and interfacial states in charge storage is proved.
【学位授予单位】：南京大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
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