基于自适应门控时钟的CPU功耗优化和VLSI设计

发布时间：2018-08-22 08:17

【摘要】：提出了一种CPU的功耗优化方法,即通过自适应时钟门控来解决CPU中由于流水线阻塞、浮点处理器(FPU)和多媒体协处理器空闲所导致的动态功耗浪费.首先,设计了模块级自适应时钟门控单元,并通过芯片内部硬件电路来自动监测上述模块是否空闲,模块空闲时时钟关闭,从而消除了不需要的时钟翻转带来的模块内部动态功耗消耗.然后,将自适应时钟门控单元应用于国产处理器Unicore-2中,对其流水线阻塞、FPU和多媒体协处理器空闲的产生进行功耗优化.最后,基于TSMC 65 nm工艺下已流片芯片的网表和寄生参数文件,通过反标芯片的波形获得电路翻转率,并用Prime Time PX工具进行了功耗仿真.仿真结果表明,利用本方法运行Dhrystone,Whestone和Stream三个典型测试程序时可获得18%~28%的功耗收益,其面积代价可以忽略,并对CPU性能没有影响.
[Abstract]:In this paper, a power optimization method for CPU is proposed, which solves the dynamic power waste caused by pipeline blocking, floating point processor (FPU) and multimedia coprocessor idle in CPU by adaptive clock gating. First of all, the module level adaptive clock gating unit is designed, and the internal hardware circuit of the chip is used to automatically monitor whether the module is idle or not, and the clock is closed when the module is idle. Thus eliminating the unnecessary clock flip caused by the dynamic power consumption within the module. Then the adaptive clock gating unit is applied to the domestic processor Unicore-2 to optimize the power consumption of the pipeline blocking FPU and the multimedia coprocessor idle generation. Finally, based on the grid table and parasitic parameter file of the chip in TSMC 65nm process, the circuit turnover rate is obtained by the waveform of the inverse chip, and the power consumption is simulated with Prime Time PX tool. The simulation results show that 18% power gain can be obtained by using this method to run three typical test programs, Dhrystone Whestone and Stream, and the area cost is negligible and has no effect on CPU performance.
【作者单位】：东南大学国家专用集成电路系统工程研究中心;
【基金】：江苏省“青蓝工程”资助项目
【分类号】：TP332

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