一种嵌入式Flash存储器的内建自测试电路的设计
发布时间：2018-08-25 12:46
【摘要】：当今众多SoC芯片都会使用FLASH存储器,而且存储器容量正在不断增加,这给芯片的测试工作带来很多困难。时至今日,业界已经为测试嵌入式存储器开发了很多算法。不过,由于FLASH存储器的擦写周期长,需要对一般的算法加以取舍和改进。本论文的撰写背景是为华虹NEC公司EF130工艺的FLASH设计一套测试方法,决定采用内建自测试(BIST)电路,可以根据测试要求选择使用MSCAN算法、棋盘格算法、对角线算法。为了节省芯片引脚,采用串并转换电路将串行输入的测试信号转成并行信号施加到待测电路。文章首先通过阐述芯片测试的原理来引出测试的一般方法,然后介绍存储器测试的特点和故障模型；接下来阐述FLASH存储器的擦写机制,然后介绍一下被测试FLASH的特征；接着交代设计方案的制定过程和完成设计的具体方法,通过编写verilog代码来实现设计,最后仿真代码,通过验证。经过芯片流片后测试,到达了预定的要求,verilog代码以软核形式已经交付客户使用。
[Abstract]:Nowadays, many SoC chips will use FLASH memory, and the memory capacity is increasing, which brings a lot of difficulties to the chip testing. Today, the industry has developed a lot of algorithms for testing embedded memory. However, due to the long writing period of FLASH memory, the general algorithm needs to be selected and improved. The background of this thesis is to design a set of test methods for FLASH of EF130 process of Huahong NEC Company. It is decided to adopt built-in self-test (BIST) circuit. According to the test requirements, we can choose MSCAN algorithm, checkerboard algorithm and diagonal algorithm. In order to save the chip pin, the serial input test signal is converted into a parallel signal to be applied to the circuit to be tested by serial parallel conversion circuit. This paper first introduces the principle of chip testing to lead to the general method of testing, then introduces the characteristics of memory testing and fault model, then describes the erasure mechanism of FLASH memory, and then introduces the characteristics of FLASH being tested. Then it explains the process of making the design scheme and the concrete method of completing the design, and realizes the design by writing the verilog code, finally simulates the code, and verifies it. After chip stream test, the required code has been delivered to customers in soft core form.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333
本文编号：2202928
[Abstract]:Nowadays, many SoC chips will use FLASH memory, and the memory capacity is increasing, which brings a lot of difficulties to the chip testing. Today, the industry has developed a lot of algorithms for testing embedded memory. However, due to the long writing period of FLASH memory, the general algorithm needs to be selected and improved. The background of this thesis is to design a set of test methods for FLASH of EF130 process of Huahong NEC Company. It is decided to adopt built-in self-test (BIST) circuit. According to the test requirements, we can choose MSCAN algorithm, checkerboard algorithm and diagonal algorithm. In order to save the chip pin, the serial input test signal is converted into a parallel signal to be applied to the circuit to be tested by serial parallel conversion circuit. This paper first introduces the principle of chip testing to lead to the general method of testing, then introduces the characteristics of memory testing and fault model, then describes the erasure mechanism of FLASH memory, and then introduces the characteristics of FLASH being tested. Then it explains the process of making the design scheme and the concrete method of completing the design, and realizes the design by writing the verilog code, finally simulates the code, and verifies it. After chip stream test, the required code has been delivered to customers in soft core form.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333
【参考文献】
相关期刊论文 前1条
1 孙华义;郑学仁;闾晓晨;王颂辉;吴焯焰;;嵌入式存储器内建自测试的一种新型应用[J];中国集成电路;2007年11期
，本文编号：2202928
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