高性能SDRAM控制器设计及软硬件结合测试
发布时间：2018-08-28 19:58
【摘要】：随着通信、多媒体技术的发展，嵌入式片上系统(SoC：System on Chip)的应用范围越来越广泛，性能要求也越来越高。嵌入式SoC的性能主要取决于嵌入式SoC内核的处理能力和存储器的带宽，而在SoC内核性能越来越高的情况下，存储器带宽成为了SoC整体性能提升的瓶颈。SDRAM凭借其快速、稳定、功耗低、支持猝发式（burst）读写等众多优良特性，成为了当今SoC外部缓存的首选。因此，，研究设计高性能SDRAM控制器有着重要的意义。 本文针对SoC芯片架构设计一款高性能SDR/DDR SDRAM控制器，通过软件测试优化性能，并在Xilinx Virtex-4XC4VLX200FPGA中实现。 本文首先介绍SDRAM存储器的基本工作原理，给出了SDRAM支持的指令和典型的操作时序，按照JEDEC SDRAM规范制定了详细的SDRAM控制器设计方案，并重点介绍了主要模块的设计方法。同时，本文介绍并比较几种常用的总线和仲裁方式，在SDRAM控制器中植入能保证带宽和读写延时的总线仲裁方式。 其次，参考典型的SDRAM存储器优化方法，在现有的SoC芯片架构下优化控制器。采用的优化方式包括：基于QoS优化多端口仲裁方式；分散刷新操作并尽可能在SDRAM处于空闲状态时进行刷新；改进映射方法来充分利用SDRAM的行缓冲区等。 最后，将该控制器集成到SoC仿真平台中，使用Cadence公司的NCVerilog对其进行仿真，分析优化结果。同时建立相应FPGA原型。 仿真和FPGA验证的结果表明：控制器达到了预定的设计指标，能够兼容多种规格的SDRAM，包括SDR、DDR。基于基准程序STREAM和直接存储器存取（DMA）的评估结果表明：SDRAM控制器优化后，系统存储器带宽提高了17.8％、性能指标提高了30.6％。
[Abstract]:With the development of communication and multimedia technology, embedded on-chip system (SoC:System on Chip) is applied more and more widely. The performance of embedded SoC mainly depends on the processing ability of embedded SoC kernel and the bandwidth of memory. However, with the increasing performance of SoC kernel, memory bandwidth has become the bottleneck of overall performance improvement of SoC. Low power consumption, support burst (burst) reading and writing, and many other excellent features, has become the first choice of SoC external cache. Therefore, it is of great significance to study and design high performance SDRAM controller. In this paper, a high performance SDR/DDR SDRAM controller is designed for SoC chip architecture. The performance is optimized by software test and implemented in Xilinx Virtex-4XC4VLX200FPGA. In this paper, the basic working principle of SDRAM memory is introduced, the instruction supported by SDRAM and the typical operation timing are given, the detailed design scheme of SDRAM controller is made according to JEDEC SDRAM specification, and the design method of main modules is introduced emphatically. At the same time, several common bus and arbitration methods are introduced and compared in this paper. The bus arbitration method which can guarantee bandwidth and read / write delay is embedded in the SDRAM controller. Secondly, referring to the typical SDRAM memory optimization method, the controller is optimized under the existing SoC chip architecture. The optimization methods adopted include: optimizing multi-port arbitration mode based on QoS; decentralized refresh operation and refresh when SDRAM is in idle state as far as possible; improving mapping method to make full use of SDRAM row buffer and so on. Finally, the controller is integrated into the SoC simulation platform, and the NCVerilog of Cadence is used to simulate the controller, and the optimization results are analyzed. At the same time, build the corresponding FPGA prototype. The results of simulation and FPGA verification show that the controller has reached the predetermined design target and can be compatible with various specifications of SDRAM, including SDR,DDR.. The evaluation results based on reference program STREAM and direct memory access (DMA) show that the memory bandwidth of the system is increased by 17.8and the performance index is improved by 30.6after the controller is optimized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
本文编号：2210455
[Abstract]:With the development of communication and multimedia technology, embedded on-chip system (SoC:System on Chip) is applied more and more widely. The performance of embedded SoC mainly depends on the processing ability of embedded SoC kernel and the bandwidth of memory. However, with the increasing performance of SoC kernel, memory bandwidth has become the bottleneck of overall performance improvement of SoC. Low power consumption, support burst (burst) reading and writing, and many other excellent features, has become the first choice of SoC external cache. Therefore, it is of great significance to study and design high performance SDRAM controller. In this paper, a high performance SDR/DDR SDRAM controller is designed for SoC chip architecture. The performance is optimized by software test and implemented in Xilinx Virtex-4XC4VLX200FPGA. In this paper, the basic working principle of SDRAM memory is introduced, the instruction supported by SDRAM and the typical operation timing are given, the detailed design scheme of SDRAM controller is made according to JEDEC SDRAM specification, and the design method of main modules is introduced emphatically. At the same time, several common bus and arbitration methods are introduced and compared in this paper. The bus arbitration method which can guarantee bandwidth and read / write delay is embedded in the SDRAM controller. Secondly, referring to the typical SDRAM memory optimization method, the controller is optimized under the existing SoC chip architecture. The optimization methods adopted include: optimizing multi-port arbitration mode based on QoS; decentralized refresh operation and refresh when SDRAM is in idle state as far as possible; improving mapping method to make full use of SDRAM row buffer and so on. Finally, the controller is integrated into the SoC simulation platform, and the NCVerilog of Cadence is used to simulate the controller, and the optimization results are analyzed. At the same time, build the corresponding FPGA prototype. The results of simulation and FPGA verification show that the controller has reached the predetermined design target and can be compatible with various specifications of SDRAM, including SDR,DDR.. The evaluation results based on reference program STREAM and direct memory access (DMA) show that the memory bandwidth of the system is increased by 17.8and the performance index is improved by 30.6after the controller is optimized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
【参考文献】
相关期刊论文 前3条
1 朱炜;刘新宁;;DDR SDRAM控制器的设计与实现[J];电子器件;2009年03期
2 李瑞;赵建明;冀力强;;基于SOC的SDRAM控制器的分析与设计[J];信息技术;2007年12期
3 熊兴中;;SDRAM内存条控制器的设计与实现[J];四川理工学院学报(自然科学版);2006年06期
相关博士学位论文 前1条
1 李文;存储控制系统性能优化技术研究[D];中国科学院研究生院（计算技术研究所）;2005年
相关硕士学位论文 前1条
1 李栋;基于SoC的实时成像处理器中DDR存储系统研究[D];中国科学院研究生院（计算技术研究所）;2004年
本文编号：2210455
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2210455.html
