基于FPGA的进位存储大数乘法器的改进与实现
发布时间：2018-08-29 14:42
【摘要】：提出了一种基于FPGA的进位存储的大数乘法器的改进算法,该算法采用串并混合结构可以在一个时钟内完成多次迭代计算,减少了完成一次运算的时钟数,因此有效地提高了大数乘法器的速度。最后硬件结构设计在Altera Stratix Ⅱ EP2S90F1508C3上实现,给出了192位、256位以及384位的乘法器性能分析,其中,192位可达到0.18μs,256位达到0.27μs,384位达到0.59μs,速度上都提高了3.5倍左右。
[Abstract]:In this paper, an improved algorithm of carry store large number multiplier based on FPGA is proposed. This algorithm can perform multiple iterations in a single clock by using a series-parallel hybrid structure, thus reducing the number of clocks to complete a single operation. Therefore, the speed of the multiplier is improved effectively. Finally, the hardware structure is implemented on Altera Stratix 鈪，
本文编号：2211521
[Abstract]:In this paper, an improved algorithm of carry store large number multiplier based on FPGA is proposed. This algorithm can perform multiple iterations in a single clock by using a series-parallel hybrid structure, thus reducing the number of clocks to complete a single operation. Therefore, the speed of the multiplier is improved effectively. Finally, the hardware structure is implemented on Altera Stratix 鈪，
本文编号：2211521
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2211521.html
