IEEE1394物理层核的设计与验证
发布时间：2018-08-29 17:59
【摘要】：随着信息技术的快速发展，人们对计算机外设的传输速度提出了更高的要求，，多种接口标准应运而生，包括USB、IEEE1394、FiberChannel、SSA、Ultra SCSI等。IEEE1394作为一种高速串行总线标准，不管是传输速度还是数据可靠性都具有很大优势。它不仅支持热拔插，还具有等时传输和异步传输两种通信方式，广泛应用于航空航天、数码摄像机、高速外接硬盘、打印机等多种设备。 本文研究的物理层IP核是IEEE1394芯片的一个子模块。它负责将数据从链路层发送到总线接口，以及将总线上接收的数据转发给链路层。本次设计的物理层IP核符合IEEE1394a协议，它实现了物理层的基本功能，传输速度最高达到400Mbps，可以单独流片或同其他协议层做成SOC产品。对IEEE1394芯片的研究工作具有一定的参考意义和实用价值。 本文首先分析了IEEE1394协议的基本内容，重点阐述了协议中有关物理层的仲裁机制和通信原理。然后根据功能要求，提出了物理层IP核的系统级解决方案，并完成了每个子模块的设计工作，同时制定了每个子模块的外部接口信号以及内部状态机描述。整个过程采用自上而下的设计思路。为了保证设计结果的正确性和可靠性，最后搭建了系统级验证平台，制定了详细验证方案，并用modelsim6.5仿真工具对设计结果进行了功能仿真，仿真结果表明此次IP核设计的功能和时序均满足协议要求。
[Abstract]:With the rapid development of information technology, people put forward higher requirements for the transmission speed of computer peripherals. A variety of interface standards emerge as the times require, including USB,IEEE1394,FiberChannel,SSA,Ultra SCSI, etc., as a high-speed serial bus standard. Both transmission speed and data reliability have great advantages. It not only supports hot plug, but also has two communication modes: isochronous transmission and asynchronous transmission. It is widely used in aerospace, digital camera, high-speed external hard disk, printer and other devices. The physical layer IP core studied in this paper is a sub-module of IEEE1394 chip. It is responsible for transmitting data from the link layer to the bus interface and forwarding the data received on the bus to the link layer. The design of the physical layer IP core accords with the IEEE1394a protocol, it realizes the basic functions of the physical layer, the transmission speed is up to 400 Mbps. it can be made into SOC products on a single stream sheet or with other protocol layers. It has certain reference significance and practical value to the research work of IEEE1394 chip. In this paper, the basic content of IEEE1394 protocol is analyzed, and the arbitration mechanism and communication principle of the physical layer in the protocol are expounded. Then, according to the functional requirements, the system-level solution of the physical layer IP core is proposed, and the design of each sub-module is completed. At the same time, the external interface signals of each sub-module and the description of the internal state machine are worked out. The whole process adopts a top-down design idea. In order to ensure the correctness and reliability of the design results, a system-level verification platform is built, a detailed verification scheme is established, and the design results are simulated with modelsim6.5 simulation tools. The simulation results show that the function and timing of the IP core design meet the requirements of the protocol.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN402
本文编号：2211974
[Abstract]:With the rapid development of information technology, people put forward higher requirements for the transmission speed of computer peripherals. A variety of interface standards emerge as the times require, including USB,IEEE1394,FiberChannel,SSA,Ultra SCSI, etc., as a high-speed serial bus standard. Both transmission speed and data reliability have great advantages. It not only supports hot plug, but also has two communication modes: isochronous transmission and asynchronous transmission. It is widely used in aerospace, digital camera, high-speed external hard disk, printer and other devices. The physical layer IP core studied in this paper is a sub-module of IEEE1394 chip. It is responsible for transmitting data from the link layer to the bus interface and forwarding the data received on the bus to the link layer. The design of the physical layer IP core accords with the IEEE1394a protocol, it realizes the basic functions of the physical layer, the transmission speed is up to 400 Mbps. it can be made into SOC products on a single stream sheet or with other protocol layers. It has certain reference significance and practical value to the research work of IEEE1394 chip. In this paper, the basic content of IEEE1394 protocol is analyzed, and the arbitration mechanism and communication principle of the physical layer in the protocol are expounded. Then, according to the functional requirements, the system-level solution of the physical layer IP core is proposed, and the design of each sub-module is completed. At the same time, the external interface signals of each sub-module and the description of the internal state machine are worked out. The whole process adopts a top-down design idea. In order to ensure the correctness and reliability of the design results, a system-level verification platform is built, a detailed verification scheme is established, and the design results are simulated with modelsim6.5 simulation tools. The simulation results show that the function and timing of the IP core design meet the requirements of the protocol.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN402
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本文编号：2211974
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