16位RISC处理器的设计和FPGA实现
发布时间：2018-09-04 20:32
【摘要】：精简指令集计算机(Reduced Instruction Set Computer, RISC)是1979年提出的一种先进的处理器设计思想,其特点为优先选取处理器中使用频率最高的指令,并将指令的格式固定,指令的寻址方式减少。由于RISC简单高效的优点,使其在提出之后就得到了业界的广泛关注。目前在高性能服务器和嵌入式领域,90%的处理器都是采用RISC架构进行设计的。但是,在RISC处理器经典的五级流水线结构中,执行阶段存在的逻辑众多,可能会产生拥堵现象,从而影响流水线的执行速率。为了避免逻辑拥堵现象的发生,进一步提高流水线的数据处理速度及扩展处理器功能,本文对处理器的流水线结构重新进行划分,提出了一种由指令取出单元(IF)、指令译码单元(ID)、控制逻辑执行单元(FLE)、运算单元(AU)和寄存器组(REF)五部分组成的新型五级流水线结构。其中,在流水线的运算单元添加了新型的乘累加器来拓展RISC处理器的功能,与普通乘累加器相比,此新型乘累加器注重电路结构的简化,并且其执行速度提升了三倍。本论文研究了流水线结构引入的结构相关、数据相关和控制相关问题,并使用哈佛结构、数据前推技术以及软件编程的方法分别解决了这三种相关性问题。在新型流水线结构的具体实现时使用Verilog HDL完成了流水线的逻辑设计,利用Modelsim软件对流水线各级以及整体结构进行了功能仿真,然后使用Quartus Ⅱ软件对处理器进行了逻辑综合以及静态时序分析。从仿真综合的结果可以看出：处理器可以平稳快速地执行,并且流水线中的每一条指令都可以在一个时钟周期内执行完毕。时序报告显示：该处理器没有发生任何时序违规现象,满足时序设计要求,并且流水线结构的最大工作频率可以达到172.95MHz,与同类设计相比,提高了15.2%。最后,在FPGA实验板上对其进行硬件调试,达到了本设计预期的目标。
[Abstract]:Reduced instruction set computer (Reduced Instruction Set Computer, RISC) is an advanced processor design idea proposed in 1979. Its characteristic is to select the most frequently-used instruction in the processor, to fix the format of instruction and to reduce the addressing mode of instruction. Because of the advantages of simple and efficient RISC, it has been widely concerned by the industry after it was put forward. At present, 90% of processors in high performance server and embedded field are designed with RISC architecture. However, in the classical five-stage pipelined architecture of RISC processor, there is a lot of logic in the execution phase, which may result in congestion, which will affect the execution rate of the pipeline. In order to avoid the phenomenon of logic congestion, further improve the data processing speed of pipeline and extend the processor function, the pipeline structure of the processor is redivided in this paper. A novel five-stage pipeline structure is proposed, which consists of five parts: the instruction extraction unit (IF), the instruction decoding unit (ID), the (ID), control logic execution unit (AU), and the register group (REF) (REF). Among them, a new multiplicative accumulator is added to the pipeline unit to expand the function of RISC processor. Compared with the ordinary multiplier accumulator, the new multiplier accumulator emphasizes the simplification of the circuit structure, and its execution speed is three times higher than that of the common multiplier accumulator. In this paper, the structural correlation, data correlation and control related problems introduced by pipeline structure are studied, and the three correlation problems are solved by using Harvard structure, data forward technology and software programming. In the realization of the new pipeline structure, Verilog HDL is used to complete the logical design of the pipeline, and the functions of the pipeline at all levels and the whole structure are simulated by using the Modelsim software. Then, the logic synthesis and static timing analysis of the processor are carried out by using Quartus 鈪，
本文编号：2223249
[Abstract]:Reduced instruction set computer (Reduced Instruction Set Computer, RISC) is an advanced processor design idea proposed in 1979. Its characteristic is to select the most frequently-used instruction in the processor, to fix the format of instruction and to reduce the addressing mode of instruction. Because of the advantages of simple and efficient RISC, it has been widely concerned by the industry after it was put forward. At present, 90% of processors in high performance server and embedded field are designed with RISC architecture. However, in the classical five-stage pipelined architecture of RISC processor, there is a lot of logic in the execution phase, which may result in congestion, which will affect the execution rate of the pipeline. In order to avoid the phenomenon of logic congestion, further improve the data processing speed of pipeline and extend the processor function, the pipeline structure of the processor is redivided in this paper. A novel five-stage pipeline structure is proposed, which consists of five parts: the instruction extraction unit (IF), the instruction decoding unit (ID), the (ID), control logic execution unit (AU), and the register group (REF) (REF). Among them, a new multiplicative accumulator is added to the pipeline unit to expand the function of RISC processor. Compared with the ordinary multiplier accumulator, the new multiplier accumulator emphasizes the simplification of the circuit structure, and its execution speed is three times higher than that of the common multiplier accumulator. In this paper, the structural correlation, data correlation and control related problems introduced by pipeline structure are studied, and the three correlation problems are solved by using Harvard structure, data forward technology and software programming. In the realization of the new pipeline structure, Verilog HDL is used to complete the logical design of the pipeline, and the functions of the pipeline at all levels and the whole structure are simulated by using the Modelsim software. Then, the logic synthesis and static timing analysis of the processor are carried out by using Quartus 鈪，
本文编号：2223249
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