边界扫描技术研究及ARM JTAG调试器的设计与实现
发布时间：2018-09-05 14:08
【摘要】：ARM处理器在现代的嵌入式电子产品中广泛应用，特别在通信、工业控制、自动化等行业更是应用广泛，目前ARM处理已经成为嵌入式电子产品中使用做多的处理器。ARM JTAG仿真器作为ARM系统开发工具链的重要组成部分之一，对软硬件开发和调试的效率、最终交付系统的稳定性和健壮性、降低系统开发难度等方面都产生重要影响。 目前，JTAG仿真器已经应用于ARM系统的软硬件研发工作之中，但高性能的JTAG调试器基本都由国外公司研发，因此价格昂贵，难以在一般开发者和小微企业普及；而国内低价的JTAG调试器由于技术方案等问题往往性能较差且不够稳定，不支持一些高级调试功能（如高速下载、硬件断点、数据断点、FLASH编程等），无法满足大规模软件开发调试的需求。 本论文正是针对上述问题，，在深入分析TAP控制器、ARM EmbeddedICE等技术的基础上，对GDB调试技术、RSP协议、μC/OS-II和LwIP等关键技术进行较深入的研究和试验，设计采用AT91SAM9260处理器芯片的ARM JTAG仿真器，全面支持ARM7和ARM9系列内核的调试、支持JTAG时钟速率可编程，具有10/100M自适应网络、USB等通信接口。本研究课题主要内容包括： 1.研究ARM JTAG调试原理，在对TAP控制器、EmbeddedICE逻辑、边界扫描链进行分析的基础之上，确定ARM JTAG仿真器的设计思路、方案以及基本实现方法。 2.在ARM JTAG调试原理的分析基础之上，提出ARM JTAG的设计需求和规格单，并基于此提出以AT91SAM9260为处理器的硬件架构的JTAG仿真器硬件设计方案，该方案支持10/100M自适应以太网、RS232串口、USB等通信接口，支持宽输入电压范围；针对被调试目标处理可能存在多种电压的实际情况，设计了具有目标处理器电压自适应能力的JTAG接口；在给出设计方案的同时，针对关键部分的电路设计给出详细的设计原理图和器件选型依据和设计原理分析。 3.按照课题的设计需求和规格要求，设计基于μC/OS-II和LwIP的软件整体架构；针对需要支持高速下载，JTAG时钟速率可编程等需求，设计了一套高性能的JTAG微指令逻辑；同时，对RSP协议、GDB命令解析器、JTAG调试命令接口等方面进行了比较详细的静态接口设计说明和动态流程设计说明。
[Abstract]:ARM processors are widely used in modern embedded electronic products, especially in communication, industrial control, automation and other industries. At present, ARM processing has become one of the most important components of the ARM system development tool chain, and the efficiency of software and hardware development and debugging has become the main part of the embedded electronic products, which uses the long processor .arm JTAG emulator as one of the most important parts of the ARM system development tool chain. The stability and robustness of the final delivery system, reducing the difficulty of system development and other aspects have an important impact. At present, JTAG emulator has been used in the research and development of ARM system, but the high performance JTAG debugger is developed by foreign companies, so it is expensive and difficult to be popularized in general developers and small and micro enterprises. However, the domestic low-cost JTAG debugger often has poor performance and unstable performance due to technical problems, so it does not support some advanced debugging functions (such as high-speed download, hardware breakpoint, etc.) Data breakpoint flash programming can not meet the needs of large-scale software development and debugging. In this paper, based on the analysis of TAP controller and arm EmbeddedICE technology, the key technologies of GDB debugging, such as GDB protocol, 渭 C/OS-II and LwIP, are studied and tested, and a ARM JTAG simulator using AT91SAM9260 processor chip is designed. It fully supports the debugging of ARM7 and ARM9 series kernels, supports the programmable clock rate of JTAG, and has 10 / 100M adaptive network communication interfaces such as USB. The main contents of this research include: 1. The principle of ARM JTAG debugging is studied. Based on the analysis of embedded ICE logic and boundary scan chain of TAP controller, the design idea, scheme and basic implementation method of ARM JTAG simulator are determined. 2. Based on the analysis of the debugging principle of ARM JTAG, the design requirements and specifications of ARM JTAG are presented, and the hardware design scheme of JTAG simulator based on AT91SAM9260 is presented. This scheme supports 10 / 100M adaptive Ethernet RS232 serial port and other communication interfaces, supports wide input voltage range, and designs a JTAG interface with the ability of adaptive voltage adaptation of target processor in view of the fact that there may be a variety of voltages to be processed by the target to be debugged. At the same time, the detailed design schematic diagram, device selection basis and design principle analysis are given for the circuit design of the key part. 3. According to the design requirements and specifications of the project, the software architecture based on 渭 C/OS-II and LwIP is designed, and a set of high-performance JTAG microinstruction logic is designed for the need to support high-speed download JTAG clock rate programmable. In this paper, the static interface design and dynamic flow design of RSP protocol are described in detail from the aspects of JTAG debug command interface and GDB command parser.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
本文编号：2224510
[Abstract]:ARM processors are widely used in modern embedded electronic products, especially in communication, industrial control, automation and other industries. At present, ARM processing has become one of the most important components of the ARM system development tool chain, and the efficiency of software and hardware development and debugging has become the main part of the embedded electronic products, which uses the long processor .arm JTAG emulator as one of the most important parts of the ARM system development tool chain. The stability and robustness of the final delivery system, reducing the difficulty of system development and other aspects have an important impact. At present, JTAG emulator has been used in the research and development of ARM system, but the high performance JTAG debugger is developed by foreign companies, so it is expensive and difficult to be popularized in general developers and small and micro enterprises. However, the domestic low-cost JTAG debugger often has poor performance and unstable performance due to technical problems, so it does not support some advanced debugging functions (such as high-speed download, hardware breakpoint, etc.) Data breakpoint flash programming can not meet the needs of large-scale software development and debugging. In this paper, based on the analysis of TAP controller and arm EmbeddedICE technology, the key technologies of GDB debugging, such as GDB protocol, 渭 C/OS-II and LwIP, are studied and tested, and a ARM JTAG simulator using AT91SAM9260 processor chip is designed. It fully supports the debugging of ARM7 and ARM9 series kernels, supports the programmable clock rate of JTAG, and has 10 / 100M adaptive network communication interfaces such as USB. The main contents of this research include: 1. The principle of ARM JTAG debugging is studied. Based on the analysis of embedded ICE logic and boundary scan chain of TAP controller, the design idea, scheme and basic implementation method of ARM JTAG simulator are determined. 2. Based on the analysis of the debugging principle of ARM JTAG, the design requirements and specifications of ARM JTAG are presented, and the hardware design scheme of JTAG simulator based on AT91SAM9260 is presented. This scheme supports 10 / 100M adaptive Ethernet RS232 serial port and other communication interfaces, supports wide input voltage range, and designs a JTAG interface with the ability of adaptive voltage adaptation of target processor in view of the fact that there may be a variety of voltages to be processed by the target to be debugged. At the same time, the detailed design schematic diagram, device selection basis and design principle analysis are given for the circuit design of the key part. 3. According to the design requirements and specifications of the project, the software architecture based on 渭 C/OS-II and LwIP is designed, and a set of high-performance JTAG microinstruction logic is designed for the need to support high-speed download JTAG clock rate programmable. In this paper, the static interface design and dynamic flow design of RSP protocol are described in detail from the aspects of JTAG debug command interface and GDB command parser.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
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