基于40nm CMOS工艺大容量eFuse的设计实现与面积优化
发布时间：2018-09-06 15:15
【摘要】：在半导体技术飞速发展的今天,芯片的生产成本日益提高,这就使得我们提高芯片的良率显得至关重要。同时,在新的工艺节点下器件生产过程中带来的偏差和仿真模型带来的偏差都更容易引起生产出的芯片的参数与最初设计的值有所偏离,从而引入了熔丝技术,由此我们可以利用电熔丝将芯片中的冗余电路替换掉失效的电路来提高良率,也可以对电路进行重新组合来实现新的功能,还可以对芯片的某些参数进行微调(TRIM)来提高芯片的性能。但是传统的熔丝技术与主流的标准CMOS工艺并不兼容,导致成本偏高,而新兴的电子可编程熔丝(eFuse)同时具有体积小、成本低、可以在封装后再进行编程等众多的优点,所以电子可编程熔丝技术成为了一个新的研究热点。 本文首先总结了eFuse当前的国内外研究现状,然后基于中芯国际40纳米低漏电CMOS工艺,从eFuse器件的类型选取入手,设计了并入并出的4K bits容量的eFuse IP,并成功地进行了流片和测试,测试结果满足设计要求。 因为eFuse的存储器特性对IP的面积要求极为严苛,所以我们又通过了一个章节的篇幅来简单介绍了一种能够使大容量eFuse的IP节省约三成面积的优化方案,其优化效果显著。
[Abstract]:With the rapid development of semiconductor technology, the production cost of chips is increasing day by day, which makes it very important for us to improve the yield of chips. At the same time, the deviation brought by the device production process under the new process node and the deviation brought by the simulation model are more likely to cause the parameters of the produced chip deviate from the original design value, so the fuse technology is introduced. As a result, we can use the electric fuse to replace the redundant circuits in the chip to improve the yield, and we can also recombine the circuits to achieve new functions. Some parameters of the chip can also be fine-tuned (TRIM) to improve the performance of the chip. However, the traditional fuse technology is not compatible with the mainstream standard CMOS process, which leads to high cost. The new electronic programmable fuse (eFuse) has many advantages, such as small size, low cost, and can be programmed after packaging. Therefore, electronic programmable fuse technology has become a new research hotspot. This paper first summarizes the current research situation of eFuse at home and abroad, then based on the SMIC 40 nm low leakage CMOS process, starting with the type selection of eFuse devices, designs the eFuse IP, with 4 K bits capacity and successfully carries out the flow sheet and test. The test results meet the design requirements. Because the memory characteristic of eFuse is very strict on the area of IP, we also introduce an optimization scheme which can save about 30% area of IP of large capacity eFuse through a chapter, and its optimization effect is remarkable.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN432;TP333
本文编号：2226747
[Abstract]:With the rapid development of semiconductor technology, the production cost of chips is increasing day by day, which makes it very important for us to improve the yield of chips. At the same time, the deviation brought by the device production process under the new process node and the deviation brought by the simulation model are more likely to cause the parameters of the produced chip deviate from the original design value, so the fuse technology is introduced. As a result, we can use the electric fuse to replace the redundant circuits in the chip to improve the yield, and we can also recombine the circuits to achieve new functions. Some parameters of the chip can also be fine-tuned (TRIM) to improve the performance of the chip. However, the traditional fuse technology is not compatible with the mainstream standard CMOS process, which leads to high cost. The new electronic programmable fuse (eFuse) has many advantages, such as small size, low cost, and can be programmed after packaging. Therefore, electronic programmable fuse technology has become a new research hotspot. This paper first summarizes the current research situation of eFuse at home and abroad, then based on the SMIC 40 nm low leakage CMOS process, starting with the type selection of eFuse devices, designs the eFuse IP, with 4 K bits capacity and successfully carries out the flow sheet and test. The test results meet the design requirements. Because the memory characteristic of eFuse is very strict on the area of IP, we also introduce an optimization scheme which can save about 30% area of IP of large capacity eFuse through a chapter, and its optimization effect is remarkable.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN432;TP333
【参考文献】
相关期刊论文 前1条
1 吴丰顺,张金松,吴懿平,郑宗林,王磊,谯锴;集成电路互连引线电迁移的研究进展[J];半导体技术;2004年09期
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