一种兼容MCS-51指令集的高速MCU的设计及实现
发布时间：2018-09-08 07:25
【摘要】：MCU（Micro Controller Unit，微控制单元）自面世以来在数字系统设计中占有重要的位置，具有集成度高、可编程性强的特点，广泛用于工业控制和SoC（System on Chip，片上系统）等数字系统设计中。但是传统上的8位MCU指令执行效率通常低于20MIPS（Million Instruction per Second，百万指令每秒），限制了其在高速计算场合中的应用。 本课题来自某公司 数模混合SoC芯片设计‖项目，该项目需要一个执行效率能达到50MIPS且兼容MCS-51指令集的MCU。所谓兼容MCS-51指令集是本MCU的指令集与MCS-51系列MCU指令集相同，可以使用普通的51开发软件（如Keil C51）进行开发。 本文首先介绍了MCS-51指令集，接着描述了本设计MCU的组织结构，设计了5级流水线结构，以单时钟周期作为指令运行单位，实现了MCU内核的高速和高效率。在设计运算单元时，本文设计了一个基于进位保留的三输入加法器，利用1个三输入加法器设计了乘法器，，该乘法器只需要4个时钟周期就能完成乘法运算。 本文改进了标准8051功耗管理模块，该管理模块不仅继承了标准8051的IDLE和STOP模式，还新加入了SUSPEND模式和多时钟源自由切换功能，这样可以使用户更有效的减少芯片功耗。 此外，本文采用TSMC0.18um工艺的Flash IP核作为程序存储器，但是该IP只能支持最高30MHz的系统时钟。本文对Flash驱动模块和逻辑控制进行了改进设计使该IP能用于50MHz的系统时钟下。 最后，为了验证设计的正确性，本文搭建出基于握手协议的仿真测试平台，调用了OVM（Open Verification Methodlogy）库。本文还搭建出基于Xilinx公司的Virtex-2Pro XC2VP30FPGA开发板验证平台，并给出了FPGA占用资源统计表。验证结果证明了设计的正确性，同时ISE综合结果显示该设计支持的时钟频率可以达到60MHz。 本文实现了兼容MCS-51指令集的MCU的高速设计，在50MHz时钟下可以达到50MIPS的峰值。同目前市场上主流高速兼容MCS-51指令集MCU产品和文献[18-21]相比，性能上有显著提高。
[Abstract]:MCU (Micro Controller Unit, micro-control unit (MCU (Micro Controller Unit,) has played an important role in the design of digital system since its inception. It has the characteristics of high integration and strong programmability. It is widely used in the design of digital systems such as industrial control and SoC (System on Chip, on-chip systems. But the traditional 8-bit MCU instruction execution efficiency is usually lower than 20MIPS (Million Instruction per Second, million instruction per second, which limits its application in high-speed computing. This topic comes from a company's digital and analog hybrid SoC chip design project, which requires a MCU. that is efficient enough to execute 50MIPS and compatible with the MCS-51 instruction set. The so-called compatible MCS-51 instruction set is that the instruction set of this MCU is the same as the MCS-51 series MCU instruction set, and can be developed with common 51 development software (such as Keil C51). This paper first introduces the MCS-51 instruction set, then describes the organization structure of the MCU, and designs a 5-stage pipelined structure. The single clock cycle is used as the instruction unit to realize the high speed and high efficiency of the MCU kernel. In the design of the operation unit, a triple-input adder based on carry reservation is designed, and a multiplier is designed using a three-input adder. The multiplier needs only four clock cycles to complete the multiplication operation. This paper improves the standard 8051 power management module, which not only inherits the IDLE and STOP modes of standard 8051, but also adds the SUSPEND mode and the free switching function of multiple clock sources, which can effectively reduce the chip power consumption. In addition, the Flash IP core of TSMC0.18um process is used as program memory, but the IP can only support the highest 30MHz system clock. In this paper, the Flash driver module and logic control are improved so that the IP can be used in the system clock of 50MHz. Finally, in order to verify the correctness of the design, this paper builds a simulation test platform based on handshake protocol, and calls the OVM (Open Verification Methodlogy) library. The verification platform of Virtex-2Pro XC2VP30FPGA development board based on Xilinx company is also built in this paper, and the statistical table of FPGA occupation resources is given. The experimental results show that the design is correct, and the ISE synthesis results show that the clock frequency can reach 60 MHz. In this paper, the high speed design of MCU compatible with MCS-51 instruction set is realized, and the peak value of 50MIPS can be achieved under the 50MHz clock. Compared with the current mainstream high speed compatible MCS-51 instruction set MCU products and literature [18-21], the performance is significantly improved.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47
本文编号：2229801
[Abstract]:MCU (Micro Controller Unit, micro-control unit (MCU (Micro Controller Unit,) has played an important role in the design of digital system since its inception. It has the characteristics of high integration and strong programmability. It is widely used in the design of digital systems such as industrial control and SoC (System on Chip, on-chip systems. But the traditional 8-bit MCU instruction execution efficiency is usually lower than 20MIPS (Million Instruction per Second, million instruction per second, which limits its application in high-speed computing. This topic comes from a company's digital and analog hybrid SoC chip design project, which requires a MCU. that is efficient enough to execute 50MIPS and compatible with the MCS-51 instruction set. The so-called compatible MCS-51 instruction set is that the instruction set of this MCU is the same as the MCS-51 series MCU instruction set, and can be developed with common 51 development software (such as Keil C51). This paper first introduces the MCS-51 instruction set, then describes the organization structure of the MCU, and designs a 5-stage pipelined structure. The single clock cycle is used as the instruction unit to realize the high speed and high efficiency of the MCU kernel. In the design of the operation unit, a triple-input adder based on carry reservation is designed, and a multiplier is designed using a three-input adder. The multiplier needs only four clock cycles to complete the multiplication operation. This paper improves the standard 8051 power management module, which not only inherits the IDLE and STOP modes of standard 8051, but also adds the SUSPEND mode and the free switching function of multiple clock sources, which can effectively reduce the chip power consumption. In addition, the Flash IP core of TSMC0.18um process is used as program memory, but the IP can only support the highest 30MHz system clock. In this paper, the Flash driver module and logic control are improved so that the IP can be used in the system clock of 50MHz. Finally, in order to verify the correctness of the design, this paper builds a simulation test platform based on handshake protocol, and calls the OVM (Open Verification Methodlogy) library. The verification platform of Virtex-2Pro XC2VP30FPGA development board based on Xilinx company is also built in this paper, and the statistical table of FPGA occupation resources is given. The experimental results show that the design is correct, and the ISE synthesis results show that the clock frequency can reach 60 MHz. In this paper, the high speed design of MCU compatible with MCS-51 instruction set is realized, and the peak value of 50MIPS can be achieved under the 50MHz clock. Compared with the current mainstream high speed compatible MCS-51 instruction set MCU products and literature [18-21], the performance is significantly improved.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47
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