基于XDSP64的多接口仿真平台设计与实现
发布时间：2018-09-08 11:55
【摘要】：XDSP64是我校自主研制的一款高性能定点DSP芯片，该款芯片拥有可配置增强型主机接口（HPI）（数据总线为32或16位）、异步传输模式(ATM)的通用测试及操作物理层接口（UTOPIA）、EMIF、多通道串口以及定时器等多种外设接口。本课题基于高性能XDSP64芯片的配套验证开发系统要求，实现了对片上多种外设接口（包括UTOPIA、HPI等）的功能验证与时序测试。 为了更好的研制、测试与应用开发这些外设接口，使得XDSP64芯片达到更高的设计要求，本文设计了基于XDSP64芯片多外设接口的软硬件协同仿真平台，以实现外部主机与DSP芯片之间的多渠道高速数据通信机制（HPI通信、UTOPIA通信等）。 本文首先在广泛调研HPI、UTOPIA等接口在DSP控制领域的实际应用的基础上，深入了解了XDSP64的体系结构，并对仿真平台的系统功能进行了全面分析。结合XDSP64芯片的接口仿真开发要求，合理构建了由主机通信系统和接口主控制器两部分构成的整个仿真平台系统架构，并分别提出了平台系统的软件、硬件设计的目标。 接着本文在充分理解USB2.0接口协议基础之上，基于Cypress公司的EZ-USBFX2芯片，设计了精炼的主机通信系统，此系统有效利用了USB2.0480Mb/s的高速数据传输特点并通过对固件、驱动程序以及仿真应用软件的设计，为整个仿真系统提供了功能完整、操作灵活的主机操作平台。 同时，本文还设计了一套可视化的主机应用软件。将复杂的接口协议访问简化为视图操作，实现了良好的人机交互。 然后，本文深入研究了XDSP64的外设接口协议。基于FPGA设计了XDSP64芯片的HPI接口、UTOPIA接口等多接口主控制器。采用了异步主机接口方法来实现主控制器与主机通信系统的通信协议，以增强仿真平台的兼容性与可扩展性。在主控制器设计中设置了专用配置寄存器，以此实现对XDSP64的内、外存空间访问、寄存器操作、XDSP64的自举以及不同接口方式的数据通信。 最后本文对系统进行了全面调试和验证，结果表明此仿真平台系统能够正确、稳定地运行，完成了对XDSP64芯片HPI接口和UTOPIA接口功能的仿真和相关时序参数的测试，达到了设计的目标。
[Abstract]:XDSP64 is a high performance fixed-point DSP chip developed by our university. The chip has a configurable enhanced host interface (HPI) (data bus is 32 or 16 bits), asynchronous transmission mode (ATM) general test and operation physical layer interface (UTOPIA) EMIF, multi-channel serial port and timer and other peripheral interfaces. Based on the requirement of verification and development system of high performance XDSP64 chip, the function verification and timing test of various peripheral interfaces (including UTOPIA,HPI, etc.) on the chip are realized. In order to better research, test and develop these peripheral interfaces, make the XDSP64 chip achieve higher design requirements, this paper designed a hardware / software co-simulation platform based on XDSP64 chip multi-peripheral interface. In order to realize the multi-channel high-speed data communication mechanism between external host computer and DSP chip (HPI communication / Utopia communication etc.). Based on the extensive investigation of the practical application of HPI,UTOPIA and other interfaces in the field of DSP control, the architecture of XDSP64 is deeply understood in this paper, and the system functions of the simulation platform are analyzed. According to the requirements of interface simulation development of XDSP64 chip, the architecture of the whole simulation platform composed of host communication system and interface master controller is constructed reasonably, and the software and hardware design goals of the platform system are put forward respectively. On the basis of fully understanding the USB2.0 interface protocol, based on the EZ-USBFX2 chip of Cypress Company, this paper designs a refined host communication system, which effectively utilizes the high-speed data transmission characteristics of USB2.0480Mb/s and makes use of the firmware. The design of driver and simulation application provides the whole simulation system with a complete and flexible host operating platform. At the same time, this paper also designed a set of visual host application software. The complex interface protocol access is simplified to view operation, and good man-machine interaction is realized. Then, this paper deeply studies the peripheral interface protocol of XDSP64. Based on FPGA, the main controller with multiple interfaces such as HPI interface and UTOPIA interface of XDSP64 chip is designed. The asynchronous host interface method is used to realize the communication protocol between the master controller and the host computer communication system, so as to enhance the compatibility and extensibility of the simulation platform. A special configuration register is set up in the design of the main controller to access the internal and external memory space of the XDSP64, the register operation XDSP64 bootstrap and the data communication of different interfaces. Finally, the system is debugged and verified, and the results show that the system can run correctly and stably. The simulation of HPI interface and UTOPIA interface function of XDSP64 chip and the test of related timing parameters are completed. The goal of the design has been achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7
[Abstract]:XDSP64 is a high performance fixed-point DSP chip developed by our university. The chip has a configurable enhanced host interface (HPI) (data bus is 32 or 16 bits), asynchronous transmission mode (ATM) general test and operation physical layer interface (UTOPIA) EMIF, multi-channel serial port and timer and other peripheral interfaces. Based on the requirement of verification and development system of high performance XDSP64 chip, the function verification and timing test of various peripheral interfaces (including UTOPIA,HPI, etc.) on the chip are realized. In order to better research, test and develop these peripheral interfaces, make the XDSP64 chip achieve higher design requirements, this paper designed a hardware / software co-simulation platform based on XDSP64 chip multi-peripheral interface. In order to realize the multi-channel high-speed data communication mechanism between external host computer and DSP chip (HPI communication / Utopia communication etc.). Based on the extensive investigation of the practical application of HPI,UTOPIA and other interfaces in the field of DSP control, the architecture of XDSP64 is deeply understood in this paper, and the system functions of the simulation platform are analyzed. According to the requirements of interface simulation development of XDSP64 chip, the architecture of the whole simulation platform composed of host communication system and interface master controller is constructed reasonably, and the software and hardware design goals of the platform system are put forward respectively. On the basis of fully understanding the USB2.0 interface protocol, based on the EZ-USBFX2 chip of Cypress Company, this paper designs a refined host communication system, which effectively utilizes the high-speed data transmission characteristics of USB2.0480Mb/s and makes use of the firmware. The design of driver and simulation application provides the whole simulation system with a complete and flexible host operating platform. At the same time, this paper also designed a set of visual host application software. The complex interface protocol access is simplified to view operation, and good man-machine interaction is realized. Then, this paper deeply studies the peripheral interface protocol of XDSP64. Based on FPGA, the main controller with multiple interfaces such as HPI interface and UTOPIA interface of XDSP64 chip is designed. The asynchronous host interface method is used to realize the communication protocol between the master controller and the host computer communication system, so as to enhance the compatibility and extensibility of the simulation platform. A special configuration register is set up in the design of the main controller to access the internal and external memory space of the XDSP64, the register operation XDSP64 bootstrap and the data communication of different interfaces. Finally, the system is debugged and verified, and the results show that the system can run correctly and stably. The simulation of HPI interface and UTOPIA interface function of XDSP64 chip and the test of related timing parameters are completed. The goal of the design has been achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7
【共引文献】
相关期刊论文 前10条
1 周剑波;巩宪锋;王长松;孙宏林;;利用FPGA和USB总线的视频图像的采集与处理系统设计[J];北京科技大学学报;2006年09期
2 李金平;颜铤;;便携式电缆故障定位仪的设计研究[J];北京联合大学学报(自然科学版);2006年02期
3 邓在辉;丁莎;;断言验证技术在IP核验证中的应用[J];毕节学院学报;2008年04期
4 张松炜;张云麟;张治中;;基于FPGA的8E1时隙交换的数字交叉IP核的实现[J];重庆邮电学院学报(自然科学版);2006年02期
5 侯佰康;张昆仑;靖永志;;基于FPGA的高速磁浮列车悬浮间隙测量系统[J];传感技术学报;2006年06期
6 靖永志;张昆仑;;高速磁浮列车悬浮气隙测量系统的设计[J];传感器技术;2005年12期
7 谢桂英;;E1/VC-4映射解映射系统的设计[J];中国城市经济;2011年03期
8 赵红梅,王召东;可编程逻辑器件FPGA与CPLD的发展与应用一例[J];平顶山工学院学报;2005年04期
9 浦索明;罗汉文;樊迅;;高速MIMO解调器的FPGA实现[J];电讯技术;2006年06期
10 张福洪;肖怀锋;方洪灿;邓朝日;;基于Nios Ⅱ的UHF RFID读写器设计与实现[J];电讯技术;2009年05期
相关会议论文 前8条
1 李燕斌;;AM调制度判别原理及其在话音静噪处理中的应用[A];全国第二届嵌入式技术联合学术会议论文集[C];2007年
2 张骋;杨力;蔡惠智;;并行DSP系统的FPGA设计[A];全国第二届嵌入式技术联合学术会议论文集[C];2007年
3 李凤麟;钟洪声;;保密通信中RS编解码的FPGA实现[A];2006中国西部青年通信学术会议论文集[C];2006年
4 钱伟康;虞菁;郭强;;基于SPARTAN3E-FPGA的多重数字时钟源的拓扑[A];全国第一届嵌入式技术联合学术会议论文集[C];2006年
5 陈亮;郝卫东;李静;陈e，
本文编号：2230444
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2230444.html
