新型DDR SDRAM存储器架构（SDDR）的设计
发布时间：2018-09-11 12:00
【摘要】：近年来,串行传输方式越来越受到重视,已经有不少串行传输取代并行传输的例子：USB取代了IEEE1284,SATA取代了PATA,PCI EXPRESS取代PCI等等。可以预见,未来串行传输将会成为数据传输方式的主流。 DDR SDRAM已经发展到了第三代,传输速度更快,功耗更低,应用范围更广。但是随着性能的不断提升,它的引脚也越来越多,成本越来越高。当并行传输方式为提高数据传输速率而增加端口引脚时,造成了成本的增加和信号间干扰的加剧,DDR SDRAM也陷入了同样的困境。 本文首先比较了不同的存储器的发展和优劣,在此基础上提出了一种新型的串行DDR SDRAM存储器架构SDDR。SDDR的设计思想主要有三部分： 1.将存储器的控制命令、地址、数据等信息打包,以消息包的方式传递信息,而不再是通过并行总线直接对存储器进行访问。 2.将原来存储器的控制器分为两部分,一部分连接主机,作为SDDR的控制器,另一部分作为存储器的一部分,完成数据的解析等操作。 3.在SDDR控制器与控制接口之间采用单向串行只写总线(OWOSB, One-way Write-Only Serial Bus)传递信息,信息只能沿着一个方向传输,而且OWOSB只用到2根,一根为上行总线,一根为下行总线。 本文完成了SDDR控制器和控制接口的设计,定义了串行只写总线OWOSB的消息传递帧格式,引入一根状态总线解决数据冲突,结合现有资源,完成了仿真验证工作。 在查阅大量资料后,完成SDDR SDRAM硬件测试平台原理图的设计,选取了芯片,完成电路板的布线和器件的焊接,采用滤波电路和磁珠隔离等提高了信号的抗干扰能力。最终完成了6层电路板的设计和调试,完成了SDDR架构的验证。
[Abstract]:In recent years, more and more attention has been paid to serial transmission. There are many examples of serial transmission replacing parallel transmission. IEEE1284,SATA replaces IEEE1284,SATA instead of PATA,PCI EXPRESS instead of PCI and so on. It can be predicted that the future serial transmission will become the mainstream of data transmission. DDR SDRAM has developed to the third generation, the transmission speed is faster, the power consumption is lower, the application scope is wider. However, with the continuous improvement of performance, it has more and more pins and higher cost. When the parallel transmission mode increases the port pin to improve the data transmission rate, the cost increases and the inter-signal interference intensifies. In this paper, the development and advantages of different memory are compared at first, and then a new serial DDR SDRAM memory architecture SDDR.SDDR is proposed in this paper. There are three main parts: 1. The control command, address, data and other information of the memory are packed, and the information is transmitted by the message packet, instead of directly accessing the memory through the parallel bus. 2. 2. The controller of the original memory is divided into two parts, one is connected to the host computer as the controller of SDDR, the other part is part of the memory to complete the operation of data parsing and so on. 3. A one-way serial write only bus (OWOSB, One-way Write-Only Serial Bus) is used to transmit information between the SDDR controller and the control interface. The information can only be transmitted along one direction, and only two OWOSB are used, one is an uplink bus and the other is a downlink bus. In this paper, the design of SDDR controller and control interface is completed, the message passing frame format of serial write-only bus OWOSB is defined, a state bus is introduced to solve the data conflict, and the simulation and verification work is completed with the existing resources. After consulting a lot of data, the schematic diagram of SDDR SDRAM hardware test platform is designed, the chip is selected, the wiring and welding of the circuit board are completed, and the anti-interference ability of the signal is improved by using filter circuit and magnetic bead isolation. Finally, the design and debugging of the six-layer circuit board are completed, and the SDDR architecture is verified.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
本文编号：2236632
[Abstract]:In recent years, more and more attention has been paid to serial transmission. There are many examples of serial transmission replacing parallel transmission. IEEE1284,SATA replaces IEEE1284,SATA instead of PATA,PCI EXPRESS instead of PCI and so on. It can be predicted that the future serial transmission will become the mainstream of data transmission. DDR SDRAM has developed to the third generation, the transmission speed is faster, the power consumption is lower, the application scope is wider. However, with the continuous improvement of performance, it has more and more pins and higher cost. When the parallel transmission mode increases the port pin to improve the data transmission rate, the cost increases and the inter-signal interference intensifies. In this paper, the development and advantages of different memory are compared at first, and then a new serial DDR SDRAM memory architecture SDDR.SDDR is proposed in this paper. There are three main parts: 1. The control command, address, data and other information of the memory are packed, and the information is transmitted by the message packet, instead of directly accessing the memory through the parallel bus. 2. 2. The controller of the original memory is divided into two parts, one is connected to the host computer as the controller of SDDR, the other part is part of the memory to complete the operation of data parsing and so on. 3. A one-way serial write only bus (OWOSB, One-way Write-Only Serial Bus) is used to transmit information between the SDDR controller and the control interface. The information can only be transmitted along one direction, and only two OWOSB are used, one is an uplink bus and the other is a downlink bus. In this paper, the design of SDDR controller and control interface is completed, the message passing frame format of serial write-only bus OWOSB is defined, a state bus is introduced to solve the data conflict, and the simulation and verification work is completed with the existing resources. After consulting a lot of data, the schematic diagram of SDDR SDRAM hardware test platform is designed, the chip is selected, the wiring and welding of the circuit board are completed, and the anti-interference ability of the signal is improved by using filter circuit and magnetic bead isolation. Finally, the design and debugging of the six-layer circuit board are completed, and the SDDR architecture is verified.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333
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