基于SPARC架构的ASIP设计与实现
发布时间：2018-09-12 11:04
【摘要】：在航天嵌入式处理机应用中，采用通用处理器或专用集成电路（ASIC）的实现方式均不能同时兼顾性能和灵活性的要求。专用指令集处理器（ASIP）平衡了专用集成电路的高性能和通用处理器的可编程特性，是针对某一特定应用或某一领域应用而专门设计的微处理器。本文围绕航天嵌入式应用专用指令集处理器的设计与实现做了以下三个方面的研究： 首先，选定SPARC架构作为专用指令集处理器实现的基础，并根据专用指令集处理器的设计方法以及FPGA硬件资源的特性对SPARC架构的系统结构和指令集结构做出了一定的精简与优化，进而提取出了一套专用的指令集。 其次，为了提高专用指令集处理器的性能，根据FPGA的资源特点，，专用指令集处理器采用了五级流水线的实现结构，并通过数据定向的技术和分支未执行的策略来分别解决流水线中的数据冒险和控制冒险。 最后，以Xilinx公司的FPGA Vertex-6XC6VLX240T为载体，对整个ASIP进行了系统仿真和综合验证，同时在该专用指令集处理器上实现了冒泡排序算法和FIR数字滤波器这两个应用。由仿真与验证结果可知，本文所设计的专用指令集处理器能够达到预期功能和时序要求，并且由于电路结构紧凑，在单片FPGA内能够集成多个专用指令集处理器核实现并行处理。
[Abstract]:In the application of aerospace embedded processor, the implementation of general purpose processor or ASIC (ASIC) can not meet the requirements of performance and flexibility at the same time. The ASIP processor (ASIP) balances the high performance of ASIC and the programmable characteristic of general-purpose processor. It is a microprocessor specially designed for a particular application or application in a certain field. This paper focuses on the design and implementation of the special instruction set processor for aerospace embedded application. Firstly, the SPARC architecture is selected as the basis of the implementation of the special instruction set processor. According to the design method of special instruction set processor and the characteristic of FPGA hardware resource, the system structure and instruction set structure of SPARC architecture are simplified and optimized, and a set of special instruction sets is extracted. Secondly, in order to improve the performance of the special instruction set processor, according to the resource characteristics of FPGA, the special instruction set processor adopts a five-stage pipeline structure. Data-oriented techniques and branch-unexecuted strategies are used to solve data risk-taking and control risks in pipeline respectively. Finally, the system simulation and comprehensive verification of the whole ASIP are carried out with the FPGA Vertex-6XC6VLX240T of Xilinx Company as the carrier. At the same time, the bubbling sorting algorithm and the FIR digital filter are implemented on the special instruction set processor. The simulation and verification results show that the designed special instruction set processor can achieve the expected function and timing requirements, and because of the compact circuit structure, it can integrate multiple special instruction set processor cores to realize parallel processing in a single FPGA.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
本文编号：2238798
[Abstract]:In the application of aerospace embedded processor, the implementation of general purpose processor or ASIC (ASIC) can not meet the requirements of performance and flexibility at the same time. The ASIP processor (ASIP) balances the high performance of ASIC and the programmable characteristic of general-purpose processor. It is a microprocessor specially designed for a particular application or application in a certain field. This paper focuses on the design and implementation of the special instruction set processor for aerospace embedded application. Firstly, the SPARC architecture is selected as the basis of the implementation of the special instruction set processor. According to the design method of special instruction set processor and the characteristic of FPGA hardware resource, the system structure and instruction set structure of SPARC architecture are simplified and optimized, and a set of special instruction sets is extracted. Secondly, in order to improve the performance of the special instruction set processor, according to the resource characteristics of FPGA, the special instruction set processor adopts a five-stage pipeline structure. Data-oriented techniques and branch-unexecuted strategies are used to solve data risk-taking and control risks in pipeline respectively. Finally, the system simulation and comprehensive verification of the whole ASIP are carried out with the FPGA Vertex-6XC6VLX240T of Xilinx Company as the carrier. At the same time, the bubbling sorting algorithm and the FIR digital filter are implemented on the special instruction set processor. The simulation and verification results show that the designed special instruction set processor can achieve the expected function and timing requirements, and because of the compact circuit structure, it can integrate multiple special instruction set processor cores to realize parallel processing in a single FPGA.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
【参考文献】
相关硕士学位论文 前2条
1 吴俊;基于RISC结构的ASIP设计[D];浙江大学;2002年
2 张海南;基于FPGA的高性能32位浮点FFT IP核的开发[D];广西大学;2008年
本文编号：2238798
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