基于SPARC v8体系结构的仿真平台的研究与设计
发布时间：2018-09-15 19:36
【摘要】：随着嵌入式系统的功能日趋强大,其应用范围正在不断扩展到生活中的各个领域,使嵌入式处理器已经成为当前计算机科学的一个研究热点。然而,由于嵌入式处理器结构的日益复杂化,导致直接进行嵌入式处理器的设计实现和与其相配套的系统软件的开发,需要消耗大量的时间和成本。 SPARC v8是一个RISC体系结构,具有高性能和可扩展的特性,在国防航天等工业中大量使用基于该体系结构的嵌入式处理器。本文基于SPARC v8的体系结构设计并实现了嵌入式处理器的仿真平台,通过该仿真平台可以对要设计的处理器进行验证,进行相关软件的开发测试。同时,该仿真平台通过定义的扩展接口,允许开发者和测试者自定义协处理器模块。 本文通过对SPARC v8体系结构进行详细的分析和总结,将仿真平台的架构划分为内核模块、指令执行模块、存储单元仿真模块、公共函数模块和接口函数模块。该仿真平台是一个指令级仿真器,采用指令队列来模拟流水线结构,并且添加了模拟时钟来模拟每个指令在执行过程中所用的时钟周期。考虑到不同用户对嵌入式处理器有不同的需求,本文在嵌入式处理器已有的功能的基础上,设计并实现了可扩展协处理器单元,并以循环冗余校验(CRC)单元作为例子,介绍如何通过调用相关的函数接口来实现自定义的协处理器模块。 最后,本文详细阐述了该仿真平台在linux操作系统下的实现过程。该仿真平台可以装载由编译器(例如sparc-elf-3.4.4)生成的可执行文件,然后使用定义的debug命令调试运行。该仿真平台已经在某嵌入式处理器的设计开发中应用。
[Abstract]:With the increasingly powerful function of embedded system, its application scope is expanding to every field of life, so embedded processor has become a research hotspot in computer science. However, due to the complexity of embedded processor architecture, the design and implementation of embedded processor and the development of corresponding system software are carried out directly. SPARC v8 is a RISC architecture with high performance and extensibility. It is widely used in defense and spaceflight industries, such as embedded processors based on this architecture. Based on the architecture of SPARC v8, the simulation platform of embedded processor is designed and implemented in this paper. The simulation platform can be used to verify the processor to be designed and to develop and test the related software. At the same time, the platform allows developers and testers to customize coprocessor modules by defining extended interfaces. By analyzing and summarizing the architecture of SPARC v8 in detail, the architecture of the simulation platform is divided into kernel module, instruction execution module, memory unit simulation module, common function module and interface function module. The simulation platform is an instruction level simulator which uses instruction queue to simulate pipelined structure and adds an analog clock to simulate the clock period used in the execution of each instruction. Considering that different users have different requirements for embedded processors, this paper designs and implements scalable coprocessor units on the basis of existing functions of embedded processors, and takes cyclic redundancy check (CRC) unit as an example. This paper introduces how to implement the custom coprocessor module by calling the related function interface. Finally, this paper describes the implementation of the simulation platform under the linux operating system in detail. The simulation platform can load executable files generated by compiler (such as sparc-elf-3.4.4), and then debug run with defined debug command. The simulation platform has been applied in the design and development of an embedded processor.
【学位授予单位】：华北电力大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP391.9;TP368.1
[Abstract]:With the increasingly powerful function of embedded system, its application scope is expanding to every field of life, so embedded processor has become a research hotspot in computer science. However, due to the complexity of embedded processor architecture, the design and implementation of embedded processor and the development of corresponding system software are carried out directly. SPARC v8 is a RISC architecture with high performance and extensibility. It is widely used in defense and spaceflight industries, such as embedded processors based on this architecture. Based on the architecture of SPARC v8, the simulation platform of embedded processor is designed and implemented in this paper. The simulation platform can be used to verify the processor to be designed and to develop and test the related software. At the same time, the platform allows developers and testers to customize coprocessor modules by defining extended interfaces. By analyzing and summarizing the architecture of SPARC v8 in detail, the architecture of the simulation platform is divided into kernel module, instruction execution module, memory unit simulation module, common function module and interface function module. The simulation platform is an instruction level simulator which uses instruction queue to simulate pipelined structure and adds an analog clock to simulate the clock period used in the execution of each instruction. Considering that different users have different requirements for embedded processors, this paper designs and implements scalable coprocessor units on the basis of existing functions of embedded processors, and takes cyclic redundancy check (CRC) unit as an example. This paper introduces how to implement the custom coprocessor module by calling the related function interface. Finally, this paper describes the implementation of the simulation platform under the linux operating system in detail. The simulation platform can load executable files generated by compiler (such as sparc-elf-3.4.4), and then debug run with defined debug command. The simulation platform has been applied in the design and development of an embedded processor.
【学位授予单位】：华北电力大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP391.9;TP368.1
【参考文献】
相关期刊论文 前8条
1 王利明,宋振宇,李明,陈渝;一个开放源码的嵌入式仿真环境——SkyEye[J];单片机与嵌入式系统应用;2003年09期
2 陈思功,秦晓,章恒，
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