基于FPGA的DDR3控制器设计与验证
发布时间：2018-09-18 10:39
【摘要】：存储器是计算机系统的重要组成部分，是决定计算机系统性能的关键设备之一。随着半导体技术的发展以及集成电路制造工艺的进步，“存储墙”问题变得更加严重，存储器难以满足处理器对数据访问和存储的高速度、高带宽、大容量的需求，限制了计算机系统的性能。DDR3SDRAM作为新一代的DDR内存，以其大容量、高速率和良好的兼容性在许多领域得到了广泛的应用。针对DDR3控制器的研究已成为当前计算机领域关注的焦点。FPGA作为可编程的逻辑器件具有结构灵活，集成度高以及开发周期短等特点。FPGA的快速发展加速了其在产品设计、原型验证等方面的应用。 本文分析了当前存储控制器的研究与发展情况，研究了DDR3技术规范JEDEC-79-3A以及相关资料。在全面掌握DDR3的结构、技术规范以及工作原理的基础上，提出了一种基于Altera公司FPGA的DDR3控制器设计方案。该方案将DDR3控制器分为控制器传输层和物理层两个部分进行设计，对各部分内部模块的功能和逻辑实现方式进行了详细的描述。本文从DDR3控制器的设计与验证等方面展开研究，，主要工作以及研究成果： 1.对DRAM的结构和工作原理接口进行了深入研究与分析，对DDR3的新特性、低功耗设计技术等进行了详细说明。对DDR3的工作原理和工作过程有了深入的理解。 2.把DDR3内存控制器的结构划分为传输层和物理层两个部分，使用Verilog对两个部分中的模块进行设计。使用Modelsim-Altera对控制器整体设计进行了功能仿真。 3.搭建了FPGA验证平台，介绍了DDR3控制器的FPGA实现过程，对控制器进行了读写功能验证以及自检测模型测试。 4.对内存控制策略进行了分析，提出了采用体内访存顺序调度的方法对访存延时进行优化的方法。
[Abstract]:Memory is an important part of computer system and one of the key equipments to determine the performance of computer system. With the development of semiconductor technology and the progress of IC manufacturing technology, the problem of "storage wall" becomes more and more serious, and the memory is difficult to meet the high speed, high bandwidth and large capacity of the processor for data access and storage. As a new generation of DDR memory, DDR3 SDRAM, which limits the performance of computer system, has been widely used in many fields with its large capacity, high speed and good compatibility. The research of DDR3 controller has become the focus in the field of computer. As a programmable logic device, it has the characteristics of flexible structure, high integration and short development cycle. The rapid development of FPGA accelerates its product design. Prototype verification and other applications. In this paper, the current research and development of memory controller are analyzed, and the DDR3 specification JEDEC-79-3A and related data are studied. On the basis of mastering the structure, technical specification and working principle of DDR3, a design scheme of DDR3 controller based on FPGA of Altera Company is presented. In this scheme, the DDR3 controller is divided into two parts: the controller transport layer and the physical layer. The function and logic implementation of each module are described in detail. In this paper, the design and verification of DDR3 controller are studied. The main work and research results are as follows: 1. The structure and working principle interface of DRAM are deeply studied and analyzed. The new characteristics of DDR3 and the low power design technology are described in detail. Have a deep understanding of the working principle and working process of DDR3. 2. The structure of DDR3 memory controller is divided into two parts: transport layer and physical layer. The modules in the two parts are designed by Verilog. Modelsim-Altera is used to simulate the overall design of the controller. 3. The FPGA verification platform is built, the FPGA implementation of the DDR3 controller is introduced, the read and write function of the controller is verified and the self-detection model is tested. 4. In this paper, the memory control strategy is analyzed, and the method of memory access sequence scheduling is proposed to optimize the memory access delay.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
本文编号：2247643
[Abstract]:Memory is an important part of computer system and one of the key equipments to determine the performance of computer system. With the development of semiconductor technology and the progress of IC manufacturing technology, the problem of "storage wall" becomes more and more serious, and the memory is difficult to meet the high speed, high bandwidth and large capacity of the processor for data access and storage. As a new generation of DDR memory, DDR3 SDRAM, which limits the performance of computer system, has been widely used in many fields with its large capacity, high speed and good compatibility. The research of DDR3 controller has become the focus in the field of computer. As a programmable logic device, it has the characteristics of flexible structure, high integration and short development cycle. The rapid development of FPGA accelerates its product design. Prototype verification and other applications. In this paper, the current research and development of memory controller are analyzed, and the DDR3 specification JEDEC-79-3A and related data are studied. On the basis of mastering the structure, technical specification and working principle of DDR3, a design scheme of DDR3 controller based on FPGA of Altera Company is presented. In this scheme, the DDR3 controller is divided into two parts: the controller transport layer and the physical layer. The function and logic implementation of each module are described in detail. In this paper, the design and verification of DDR3 controller are studied. The main work and research results are as follows: 1. The structure and working principle interface of DRAM are deeply studied and analyzed. The new characteristics of DDR3 and the low power design technology are described in detail. Have a deep understanding of the working principle and working process of DDR3. 2. The structure of DDR3 memory controller is divided into two parts: transport layer and physical layer. The modules in the two parts are designed by Verilog. Modelsim-Altera is used to simulate the overall design of the controller. 3. The FPGA verification platform is built, the FPGA implementation of the DDR3 controller is introduced, the read and write function of the controller is verified and the self-detection model is tested. 4. In this paper, the memory control strategy is analyzed, and the method of memory access sequence scheduling is proposed to optimize the memory access delay.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
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相关期刊论文 前2条
1 俞吉波;孔雪;郑哲;祝永新;付宇卓;;FPGA实际可用性评估与发展趋势分析[J];计算机工程;2011年13期
2 周昆正;基于FPGA的SDRAM控制器设计[J];现代电子技术;2003年13期
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