通用高性能微处理器的低功耗片上存储系统研究
发布时间：2018-09-19 17:54
【摘要】：微处理器是片上系统（SoC）的核心,其低功耗设计对整个系统的重要性突出，而低功耗片上存储系统的设计是最重要的研究领域之一，是实现低功耗微处理器的关键，因为超过60％的功耗在微处理器芯片的片上存储系统中产生。 本文给出一种新型SRAM单元，，在读操作过程中其数据具有较高的稳定性，并且与传统4管SRAM单元和6管SRAM单元相比具有更高的静态噪声容限，另外也弥补了传统SRAM存在的两方面缺陷。7管SRAM单元的数据读写路径独立，读写过程的相互干扰也由此避免。特别地，由于去除了从位线到存储节点的直接通路，到达了隔离数据的目的。因此，外部噪声不易破坏SRAM单元中的数据，从而提高SRAM单元抗外部噪声的性能和数据稳定度。仿真采用TSMC1-Poly6-Metals0.18-μm CMOS工艺，在给定模式下，V_(DD)=1.8V，温度T=25℃。仿真表明，7管SRAM单元的读静态噪声容限高达1.43V，比传统4管和6管SRAM单元显著增加1.6倍和0.31倍。 为了实现低功耗的目的，本文给出一种只含一位标识的片上指令Cache。在微处理器中，由于片上I-Cache大面积与极高频率地被读取，其功耗占据相当大部分。为了减少片上I-Cache的功耗，本文研究了一种一位标识符的片上I-Cache。改进后的I-Cache在面积上显著减少，Cache标识部分只保留最根本的一位。同时，为了配合只含一位标识的片上I-Cache，使程序依然有效地执行，本文又给出一种Cache操作控制机制。对于大多数应用程序而言，一位标识Cache可以达到与传统全标识Cache相似的性能，但由于Cache面积急剧减少，并衍生规模更小的标识(Tag)阵列与更少的Tag比较电路，所以可以有效降低功耗。
[Abstract]:Microprocessor is the core of on-chip system (SoC), and its low power design is very important to the whole system. The design of low power on-chip memory system is one of the most important research fields, and it is the key to realize low power microprocessor. Because more than 60% of the power consumption is generated in the on-chip memory system of the microprocessor chip. In this paper, a new type of SRAM unit is presented. Its data is stable in the process of reading operation, and it has higher static noise tolerance than the traditional 4-tube SRAM unit and 6-tube SRAM unit. In addition, it also makes up for the two defects of traditional SRAM. 7. The data read-write path of SRAM cell is independent, and the mutual interference of reading and writing process is avoided. In particular, the purpose of isolating data is achieved by removing the direct path from bit lines to storage nodes. Therefore, the external noise is not easy to destroy the data in the SRAM unit, thus improving the performance and data stability of the SRAM unit against external noise. The TSMC1-Poly6-Metals0.18- 渭 m CMOS process is used in the simulation. Under the given mode, the temperature of V _ (DD) is 1.8 V and the temperature is 25 鈩
本文编号：2250889
[Abstract]:Microprocessor is the core of on-chip system (SoC), and its low power design is very important to the whole system. The design of low power on-chip memory system is one of the most important research fields, and it is the key to realize low power microprocessor. Because more than 60% of the power consumption is generated in the on-chip memory system of the microprocessor chip. In this paper, a new type of SRAM unit is presented. Its data is stable in the process of reading operation, and it has higher static noise tolerance than the traditional 4-tube SRAM unit and 6-tube SRAM unit. In addition, it also makes up for the two defects of traditional SRAM. 7. The data read-write path of SRAM cell is independent, and the mutual interference of reading and writing process is avoided. In particular, the purpose of isolating data is achieved by removing the direct path from bit lines to storage nodes. Therefore, the external noise is not easy to destroy the data in the SRAM unit, thus improving the performance and data stability of the SRAM unit against external noise. The TSMC1-Poly6-Metals0.18- 渭 m CMOS process is used in the simulation. Under the given mode, the temperature of V _ (DD) is 1.8 V and the temperature is 25 鈩
本文编号：2250889
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