YHFT-Matrix高性能DSP软核中DMA控制器的设计与验证
发布时间：2018-10-07 19:37
【摘要】：YHFT-Matrix是国防科大研发的具有自主知识产权的面向无线通信、视频和图像处理的高性能浮点DSP(Digital Signal Processor)软核。为解决DSP的数据供给问题,本文设计了一个功能强大的搬移数据的部件——直接存储器访问控制器(Direct Memory Access Controller,DMAC)。本文主要工作和成果包括:1.深入分析该DSP的体系结构和应用需求,完成了一个多通道多总线的DMA控制器的整体结构设计,并对DMA控制器的地址作了参数化设计。2.为满足核内的向量存储器和核外存储器的通信需求,本文设计了两个高低优先级的通用通道。它们支持矩阵转置操作,解决了现有DSP不能直接支持矩阵转置操作的难题。并且它们具有通道链接和参数连接的功能,能够满足某些复杂数据流的传输需求。3.为满足VM、ASRAM、DDR3和从天线收发数据的专用外设的通信需求,本文设计了AXI专用通道。它既可与AXI主机相连,也可与AXI从机相连,使用灵活。4.为满足仿真/调试部件ET对DSP存储空间的读写需求,本文设计了一个ET专用通道。它支持多个数据的读写并且寻址方式多样,便于以后ET功能的扩展。5.为保证设计的功能正确性,本文采用模拟验证和基于断言的验证两种验证方法对设计进行了充分验证。模拟验证分为模块级、部件级和系统级三个层次,统计的代码覆盖率满足要求。基于断言的验证对接口协议和总线仲裁进行了验证。验证结果表明,DMA控制器的功能正确,满足系统设计要求。6.基于45nm工艺库对设计进行了逻辑综合。综合结果表明,DMA控制器工作频率可达到800MHz以上,总面积为165411.5um2,总功耗为65.97 m W,达到了预期设计目标。
[Abstract]:YHFT-Matrix is a high performance floating point DSP (Digital Signal Processor) soft core with independent intellectual property for wireless communication, video and image processing developed by the University of National Defense Science and Technology. In order to solve the data supply problem of DSP, this paper designs a powerful component of moving data, called Direct memory access Controller (Direct Memory Access Controller,DMAC). The main work and results of this paper include: 1. The architecture and application requirements of the DSP are analyzed in depth. The overall structure design of a multi-channel and multi-bus DMA controller is completed, and the address of the DMA controller is parameterized. In order to meet the communication requirements of vector memory and external memory in the core, two common channels with high priority and high priority are designed in this paper. They support matrix transpose operation and solve the problem that existing DSP can not directly support matrix transpose operation. And they have the function of channel link and parameter connection, which can meet the transmission requirement of some complex data stream. 3. In order to meet the communication requirements of VM,ASRAM,DDR3 and special peripheral equipment for receiving and transmitting data from antenna, a special channel for AXI is designed in this paper. It can be connected to both the AXI host and the AXI slave, using flexible. 4. 4. In order to meet the requirement of reading and writing DSP storage space in ET, a special ET channel is designed in this paper. It supports multiple data reading, writing and addressing in a variety of ways, making it easy to extend the ET function in the future. 5. In order to ensure the functional correctness of the design, two verification methods, simulation verification and assertion based verification, are used to fully verify the design. Simulation verification is divided into three levels: module level, component level and system level. Verification based on assertion verifies interface protocol and bus arbitration. The verification results show that the function of DMA controller is correct and meets the requirement of system design. The logic synthesis of the design based on 45nm process library is carried out. The results show that the operating frequency of the controller can reach above 800MHz, the total area is 165411.5um2, the total power consumption is 65.97mW, and the expected design goal is achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
，
本文编号：2255425
[Abstract]:YHFT-Matrix is a high performance floating point DSP (Digital Signal Processor) soft core with independent intellectual property for wireless communication, video and image processing developed by the University of National Defense Science and Technology. In order to solve the data supply problem of DSP, this paper designs a powerful component of moving data, called Direct memory access Controller (Direct Memory Access Controller,DMAC). The main work and results of this paper include: 1. The architecture and application requirements of the DSP are analyzed in depth. The overall structure design of a multi-channel and multi-bus DMA controller is completed, and the address of the DMA controller is parameterized. In order to meet the communication requirements of vector memory and external memory in the core, two common channels with high priority and high priority are designed in this paper. They support matrix transpose operation and solve the problem that existing DSP can not directly support matrix transpose operation. And they have the function of channel link and parameter connection, which can meet the transmission requirement of some complex data stream. 3. In order to meet the communication requirements of VM,ASRAM,DDR3 and special peripheral equipment for receiving and transmitting data from antenna, a special channel for AXI is designed in this paper. It can be connected to both the AXI host and the AXI slave, using flexible. 4. 4. In order to meet the requirement of reading and writing DSP storage space in ET, a special ET channel is designed in this paper. It supports multiple data reading, writing and addressing in a variety of ways, making it easy to extend the ET function in the future. 5. In order to ensure the functional correctness of the design, two verification methods, simulation verification and assertion based verification, are used to fully verify the design. Simulation verification is divided into three levels: module level, component level and system level. Verification based on assertion verifies interface protocol and bus arbitration. The verification results show that the function of DMA controller is correct and meets the requirement of system design. The logic synthesis of the design based on 45nm process library is carried out. The results show that the operating frequency of the controller can reach above 800MHz, the total area is 165411.5um2, the total power consumption is 65.97mW, and the expected design goal is achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
，
本文编号：2255425
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