一款高性能处理器的可测性设计与实现
发布时间：2018-10-10 09:50
【摘要】：随着深亚微米(DSM, Deep Sub-Micron)技术和IP (Intellectual Property)核复用技术为支撑的片上系统SoC (System-on-Chip)技术的迅速发展,高性能处理器的可测试性设计(DFT, Design For Testability)已经成为了设计过程中的重要一环,成为了一项极具挑战性的工作。 本课题主要是实现了一款高性能处理器的DFT设计,该芯片采用45nm设计工艺,主频1.2GHz。芯片不仅自身逻辑模块结构复杂,而且使用了DDR3、 PCIE、 SATA、USB等高速IP核,这就给处理器的可测试性设计带来了更大的挑战。为达到芯片的测试目标和提高芯片的易测性,我们采取的DFT方法主要包括：扫描设计、存储器内建自测试、边界扫描设计,这些技术为该芯片提供了方便可靠的测试方案。 在简单论述了可测性设计的基本理论、方法和芯片的整体结构后,本文主要阐述了处理器可测性设计的实现,并且针对实现过程中的一些难点和重点做了详细的阐述,本文的主要工作和创新点总结如下： 1、在at-speed测试方案下,结合DFT方法,通过解决时钟域、门控时钟以及压缩逻辑等复杂问题,使芯片Transition故障覆盖率达到了90%左右,Stuck-at故障覆盖率达到了96.31%,达到了预期的测试要求。 2、扫描设计通过“低功耗填充”技术,有效的生成低功耗的测试向量,该技术将测试向量的每个关注位的值复制到扫描链中的后续位,直到下一个具有相反值关注位出现为止,产生低功耗的测试向量,该设计方法使单个模块的扫描功耗比正常情况下平均降低了22.46%。 3、由于芯片内的存储器数目繁多,如果用一般的设计方法,MBIST的测试功耗将非常高。而本文采取了一种降低MBIST功耗的设计方法,该方法根据时钟域、存储器大小将存储器分成不同的组,组之间进行串行测试,组内并行测试,该方法使得测试功耗与传统的测试功耗相比降低了14.36%。 目前该芯片的DFT设计工作已经全部结束,芯片正处于流片阶段,整个芯片的DFT结构已经全部通过模拟验证,证明整个设计符合测试要求。
[Abstract]:With the rapid development of deep submicron (DSM, Deep Sub-Micron technology and SoC (System-on-Chip) technology supported by IP (Intellectual Property) core reuse technology, the testability design (DFT, Design For Testability) of high performance processors has become an important part of the design process. Has become a very challenging job. The main task of this paper is to implement the DFT design of a high performance processor. The chip adopts 45nm design technology and the main frequency is 1.2 GHz. The chip not only has complex logic module structure, but also uses high speed IP core such as DDR3, PCIE, SATA,USB, which brings more challenges to the testability design of the processor. In order to achieve the test goal of the chip and improve the testability of the chip, the DFT methods we adopt mainly include: scan design, memory built-in self-test, and boundary scan design. These technologies provide a convenient and reliable test scheme for the chip. After briefly discussing the basic theory, method and the whole structure of the chip, this paper mainly describes the realization of the testability design of the processor, and gives a detailed description of some difficulties and emphases in the process of implementation. The main work and innovations of this paper are summarized as follows: 1. Under the at-speed test scheme, combining with the DFT method, the complex problems such as clock domain, gated clock and compression logic are solved. The fault coverage of chip Transition reaches about 90% and the coverage rate of Stuck-at reaches 96.31, which meets the expected test requirements. 2. The scan design effectively generates low-power test vectors through "low-power fill" technology, which copies the value of each concern bit of the test vector to a subsequent bit in the scan chain until the next one with the opposite value of concern appears. A low power test vector is generated, and the scanning power consumption of a single module is reduced by 22.46 than normal. 3. Because of the large number of memory in the chip, the test power consumption of MBIST will be very high if the general design method is used. In this paper, we adopt a design method to reduce the power consumption of MBIST. According to the clock domain and memory size, the memory is divided into different groups. This method reduces the test power consumption by 14.36 compared with the traditional test power. At present, the DFT design of the chip has been completed, the chip is in the flow stage, and the DFT structure of the whole chip has been verified by simulation, which proves that the whole design meets the test requirements.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47
本文编号：2261317
[Abstract]:With the rapid development of deep submicron (DSM, Deep Sub-Micron technology and SoC (System-on-Chip) technology supported by IP (Intellectual Property) core reuse technology, the testability design (DFT, Design For Testability) of high performance processors has become an important part of the design process. Has become a very challenging job. The main task of this paper is to implement the DFT design of a high performance processor. The chip adopts 45nm design technology and the main frequency is 1.2 GHz. The chip not only has complex logic module structure, but also uses high speed IP core such as DDR3, PCIE, SATA,USB, which brings more challenges to the testability design of the processor. In order to achieve the test goal of the chip and improve the testability of the chip, the DFT methods we adopt mainly include: scan design, memory built-in self-test, and boundary scan design. These technologies provide a convenient and reliable test scheme for the chip. After briefly discussing the basic theory, method and the whole structure of the chip, this paper mainly describes the realization of the testability design of the processor, and gives a detailed description of some difficulties and emphases in the process of implementation. The main work and innovations of this paper are summarized as follows: 1. Under the at-speed test scheme, combining with the DFT method, the complex problems such as clock domain, gated clock and compression logic are solved. The fault coverage of chip Transition reaches about 90% and the coverage rate of Stuck-at reaches 96.31, which meets the expected test requirements. 2. The scan design effectively generates low-power test vectors through "low-power fill" technology, which copies the value of each concern bit of the test vector to a subsequent bit in the scan chain until the next one with the opposite value of concern appears. A low power test vector is generated, and the scanning power consumption of a single module is reduced by 22.46 than normal. 3. Because of the large number of memory in the chip, the test power consumption of MBIST will be very high if the general design method is used. In this paper, we adopt a design method to reduce the power consumption of MBIST. According to the clock domain and memory size, the memory is divided into different groups. This method reduces the test power consumption by 14.36 compared with the traditional test power. At present, the DFT design of the chip has been completed, the chip is in the flow stage, and the DFT structure of the whole chip has been verified by simulation, which proves that the whole design meets the test requirements.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47
【参考文献】
相关期刊论文 前1条
1 蒋敬旗,周旭,李文,范东睿;系统芯片中低功耗测试的几种方法[J];微电子学与计算机;2002年10期
，本文编号：2261317
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