高密度存储服务器高速链路设计与仿真
发布时间：2018-10-12 13:40
【摘要】：针对高密度存储服务器中高速链路结构复杂、信号速率高、链路长度长等特点,在高速链路PCIE3.0和SAS3.0设计过程中引入全面的信号完整性仿真。通过对高速印刷电路板设计中拓扑结构、材料类型、印刷电路板结构等关键项目进行仿真设计,获得成本最低、性能达标的最优方案;通过全链路有源仿真,预估系统性能,降低系统投产风险;通过系统实际信号测试,验证系统性能完全满足相应规范要求,仿真结果有效可靠。
[Abstract]:In view of the characteristics of high speed link structure, high signal rate and long link length in high density storage server, comprehensive signal integrity simulation is introduced into the design process of high speed link PCIE3.0 and SAS3.0. By simulating the key items in the design of high speed printed circuit board, such as topology structure, material type, printed circuit board structure and so on, the optimal scheme with the lowest cost and up to standard performance is obtained, and the system performance is estimated by the full link active simulation. It can reduce the risk of system putting into production and verify that the performance of the system can meet the requirements of the corresponding specification and the simulation result is effective and reliable through the testing of the actual signal of the system.
【作者单位】： 北京科技大学计算机与通信工程学院;曙光信息产业有限公司;哈尔滨工程大学水声工程学院;中国科学院微电子研究所;
【基金】：国家“863”高技术研究发展计划基金资助项目(2013AA01A209) 北京市科委计划项目(D141100003414002)
【分类号】：TP333
本文编号：2266326
[Abstract]:In view of the characteristics of high speed link structure, high signal rate and long link length in high density storage server, comprehensive signal integrity simulation is introduced into the design process of high speed link PCIE3.0 and SAS3.0. By simulating the key items in the design of high speed printed circuit board, such as topology structure, material type, printed circuit board structure and so on, the optimal scheme with the lowest cost and up to standard performance is obtained, and the system performance is estimated by the full link active simulation. It can reduce the risk of system putting into production and verify that the performance of the system can meet the requirements of the corresponding specification and the simulation result is effective and reliable through the testing of the actual signal of the system.
【作者单位】： 北京科技大学计算机与通信工程学院;曙光信息产业有限公司;哈尔滨工程大学水声工程学院;中国科学院微电子研究所;
【基金】：国家“863”高技术研究发展计划基金资助项目(2013AA01A209) 北京市科委计划项目(D141100003414002)
【分类号】：TP333
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1 仇广煜,刘光明;高性能低成本的并行链路研究[J];计算机工程与科学;2001年06期
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