4-bit SONOS存储器多值存储技术及器件物理研究

发布时间：2018-10-13 17:59

【摘要】：近年来具有低电压、低成本和高可靠性等优点的电荷俘获型存储器得到广泛研究,电荷俘获型存储器成为将来可能取代传统浮栅型快闪存储器的一种可选方案。氮化硅只读存储器(NROM)作为一种独特的局部电荷俘获型多晶硅-二氧化硅-氮化硅-二氧化硅-硅(SONOS)存储器,同时运用了多位和多值编程技术,实现了每单元4比特的存储,大大提高了存储密度。然而随着存储单元沟道长度减小到90nm, NROM存储器面临诸多问题：浅沟槽隔离(STI)工艺严重影响了NROM边角单元的性能；第二位比特效应严重影响了NROM单元的多位存储特性；多值存储单元的耐受力和保持特性进一步退化；电荷保持机制依然不十分确定等等。本论文针对这些问题,开展了一系列研究工作,获得的主要成果有： (1)实验发现靠近STI的NROM边角单元的沟道热电子注入编程效率明显低于远离STI的中心单元,且边角和中心单元的初始阈值电压分布表现出明显不一致。借助于TCAD工艺仿真,发现STI引起的硼析出效应降低了边角单元有源区的硼浓度,是边角单元编程效率降低的主要原因。同时发现更高的STI压应力降低了边角单元有源区电子迁移率,它和硼析出效应共同导致了边角与中心单元初始阈值电压分布不一致。为了减小STI对边角单元的影响,提出在STI区域增加一道额外的硼注入作为解决方法。通过调节硼注入的剂量和能量,边角单元有源区的硼浓度得到了补偿,边角单元获得了和中心单元几乎相同的编程效率。此外,额外的硼注入使STI压应力和硼析出对阈值电压的影响相互抵消,边角单元和中心单元初始阈值电压分布不一致问题也得到了消除。 (2)实验发现传统沟道热电子注入(CHEI)编程受到二次热电子注入效应的影响,热电子注入分布比带-带隧穿的热空穴注入分布宽,注入的部分电子不能被有效擦除。经过多次编程／擦除循环后,残余电荷逐渐堆积,加重了单元的第二位比特效应,同时使单元耐受力和保持性能发生严重的退化。为了抑制二次热电子注入,获得注入电子和空穴分布的匹配,提出了一种改进的衬底正偏压CHEI编程。与传统的CHEI编程相比,器件的衬底接1.5V的正电压代替0V,有效地抑制了二次热电子注入。同时器件的源极接1V电压,防止了源极/衬底之间的PN结正偏,大大降低了编程的功耗。实验结果表明该编程方法使NROM器件的耐受力和保持性能得到很大的提高,第二位比特效应得到有效的抑制。该编程方法与NROM采用的幅值递增式脉冲编程技术相兼容,可直接用于4比特/单元的NROM产品实现多值/多位的编程。 (3)提出了一种新颖的高密度8值单元编程方法。该编程方法首先进行双边带-带隧穿热空穴注入的擦除,带-带隧穿产生的空穴均匀注入到器件沟道上方的存储层中,将NROM器件擦除到阈值电压为-0.5V的状态。然后以负阂值电压为新的初始状态进行局部的编程和擦除操作,得到8值存储状态,实现每个单元存储3比特。实验结果表明该8值单元存储窗口比4值单元存储窗口几乎扩大了1倍,经过1000次编程/擦除循环操作后依然具有较大的读出窗口,具有较好的耐受力和保持特性。 (4)研究了NROM器件的电荷流失机制,证实了电荷横向流失的数据保持模型。实验发现当注入的电子和空穴分布相匹配时,注入的电子可以被有效地擦除,电荷在存储层呈一极分布,从而获得了极好的保持特性。当注入的电子比注入的空穴分布宽,注入电子不能被完全擦除。经过多次编程/擦除后,残余电子和空穴逐渐堆积,形成电子-空穴-电子的三极分布。由于空穴的陷阱能级比电子低0.3eV,积累的空穴更容易通过Frenkle-Poole机制从陷阱中激发到导带,然后在氮化硅存储层中横向扩展和注入的电子发生复合,从而导致了保持性能发生严重的退化。实验同时表明当注入电子和空穴分布匹配时,增加隧穿氧化层缺陷和界面态密度并不会使保持特性发生明显的退化,从而进一步证实界面态退火和氧化层正电荷辅助隧穿不是电荷流失的主要机制,而电荷在氮化硅中的横向扩展分布才是电荷流失的主要原因。
[Abstract]:Charge trapping type memories, which have the advantages of low voltage, low cost and high reliability have been widely studied in recent years, and the charge trapping type memory becomes an alternative to replace the traditional floating gate flash memory in the future. The silicon nitride read-only memory (NROM) is a unique local charge trapping type polysilicon-silicon nitride-silicon dioxide-silicon (SONOS) memory. At the same time, multi-bit and multi-value programming technology is applied to realize the storage of 4 bits per unit, and the storage density is greatly improved. However, as the channel length of memory cell decreases to 90nm, the NROM memory is faced with many problems: shallow trench isolation (STI) process seriously affects the performance of the corner cell of the NROM, and the second bit effect seriously affects the multi-bit storage characteristic of the NROM cell. the endurance and retention characteristics of the multi-value storage unit are further degraded; the charge retention mechanism remains uncertain and the like. In view of these problems, the thesis carries out a series of research work, and the main achievements are: (1) The experimental results show that the channel hot electron injection programming efficiency of the NROM corner cell near the STI is significantly lower than that of the STI. the initial threshold voltage distribution of the corner and center cells exhibits a significant non-uniformity, By means of TCAD process simulation, it is found that the boron precipitation effect caused by STI reduces the boron concentration in the active area of corner cell, and it is the main factor of reducing the programming efficiency of corner cell. At the same time, it is found that the higher STI compressive stress reduces the electron mobility of the active region of the corner cell, which causes the initial threshold voltage distribution of the corner and the center cell to be different due to the boron precipitation effect. In order to reduce the influence of small S TI on corner elements, an additional boron implantation in STI region is proposed as a solution. Methods: By adjusting the dosage and energy of boron implantation, the boron concentration of the active region of the corner cell was compensated, and the corner cell was almost the same as the center cell. In addition, the effects of the additional boron implantation on the threshold voltage of the STI compressive stress and the boron precipitation cancel each other, and the initial threshold voltage distribution of the corner cell and the center cell is not consistent, and the problem is also obtained (2) The experimental results show that the traditional channel hot electron injection (CHEI) programming is affected by the secondary hot electron injection effect, and the hot electron injection distribution is wider than that of the hot hole injection. After multiple programming/ erase cycles, the residual charge gradually builds up, the second bit effect of the cell is aggravated, and meanwhile, the unit stress resistance and the holding performance are caused to occur. In order to suppress secondary hot electron injection, to obtain the matching of injection electron and hole distribution, an improved substrate positive bias C was proposed. HEI is programmed. Compared with the traditional CHEI programming, the substrate of the device is connected with a positive voltage of 1. 5V instead of 0V, and the secondary battery is effectively restrained. the source electrode of the device is connected with the 1V voltage, so that the PN junction between the source electrode and the substrate is prevented from being biased, The experimental results show that the programming method greatly improves the stress resistance and the holding performance of the NROM device, and the second bit effect is obtained. The programming method is compatible with the amplitude increment pulse programming technology adopted by the NROM, and can be directly used for realizing the multi-value of the NROM product of 4 bits/ unit. multi-bit programming. (3) a novel high density is proposed The programming method comprises the following steps: firstly carrying out double-sided tape-tunneling through hot hole injection erasing, uniformly injecting holes generated by the strip-and-band tunneling through into a storage layer above the device channel, and erasing the NROM device to the threshold voltage.-0. 5V state. Then perform local program and erase operation with negative ripple value voltage as the new initial state to obtain 8-value memory state, and realize each The experimental results show that the 8-value cell storage window is almost 1 times larger than the 4-value cell storage window. After 1000 times of programming/ erase cycle operation, it still has a large read-out window, and it has better performance. The electric charge loss mechanism of the NROM device is studied, and the charge is confirmed. The experimental results show that when the injected electrons and holes are matched, the injected electrons can be effectively erased, and the charge is distributed in a polar distribution in the storage layer. while the injected electrons are wider than the injected hole distribution, The injected electrons cannot be completely erased. After multiple programming/ erasing, the residual electrons and holes gradually accumulate to form electrons hole-electron tripolar distribution. Since the trap level of the hole is 0. 3eV lower than that of electrons, the accumulated holes are more likely to be excited from the trap to the conduction band through the Frenkle-Poole mechanism, and then the electrons laterally spread and injected in the silicon nitride storage layer are compounded, resulting in At the same time, it is shown that when injecting electron and hole distribution, the defect of tunneling through oxide layer and the density of interface state do not degrade the holding characteristic, so as to further confirm the interface state annealing and the positive charge auxiliary tunnel of oxide layer. It is not the main mechanism of charge loss, and the lateral expansion distribution of electric charges in silicon nitride
【学位授予单位】：南京大学
【学位级别】：博士
【学位授予年份】：2012
【分类号】：TP333

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