基于65nm工艺的寄存器堆设计技术研究
发布时间：2018-10-13 20:31
【摘要】：工艺的发展使得处理器的速度不断加快,采用流水线、超标量和超长指令字等设计方法使得处理器越来越复杂,这些变化对寄存器堆提出了更高的要求,使得寄存器堆不仅需要具有较高的性能和较小的功耗而且需要具有多端口读写能力。而且,随着工艺的进步,工艺波动导致的影响越来越严重,尤其对于寄存器堆这种决定处理器性能的部件的影响尤为明显,所以要求寄存器堆同时也具有较高的鲁棒性。此外,由于医学及无线传感器等领域的发展,要求处理器可以工作于更低电压以大幅度减小功耗,所以低电压寄存器堆设计成为一个重要的研究课题。本文主要侧重于设计高性能、低功耗、多端口的寄存器堆,并对亚阈值电压下多端口寄存器堆进行了研究与设计。 本文采用全定制的设计方法,在TSMC65nm CMOS LP工艺下,对寄存器堆的设计进行了深入的研究,设计并实现了具有4个读端口2个写端口32x32b规模寄存器堆。 本文首先对寄存器堆进行了初步的研究设计,提出了可以减小功耗并增强鲁棒性的寄存器堆输出模块,芯片测试结果显示该版本的寄存器堆可以非常稳定的工作。在1.2V电压下,功耗仅7.2mW。同时设计了一种采用灵敏放大器结构的寄存器堆,并提出了可以改变读位线摆幅的结构。 其次本文深入研究并设计了采用更小面积的存储单元和时钟脉冲控制字线的方式,实现了一款面积仅0.01mm2的寄存器堆。芯片测试结果显示,在1.2V情况下,芯片的工作频率为1.56GHz下,寄存器堆消耗功耗11.8mW。若不考虑建立时间等因素,则1.2V下寄存器堆最高工作频率约为2GHz。 本文最后对亚阈值电压下的寄存器堆进行了研究与设计。首先对亚阈值下CMOS的工作状态进行了分析,然后基于亚阈值电压下CMOS电路的工作状态,提出了新的存储单元,并采用与之前完全不同的读写方法设计了多端口的寄存器堆。
[Abstract]:With the development of technology, the speed of processor is speeding up. The design methods such as pipeline, superscalar and ultra-long instruction word make the processor more and more complex. These changes put forward higher requirements to register file. The register file needs not only high performance and low power consumption, but also multi-port reading and writing ability. Moreover, with the progress of process, the effect of process fluctuation is becoming more and more serious, especially for register file, which determines the processor performance, so the register file is required to be robust at the same time. In addition, due to the development of medicine and wireless sensor, it is required that the processor can work at lower voltage to greatly reduce power consumption, so the design of low voltage register file has become an important research topic. This paper focuses on the design of high performance, low power, multi-port register file, and the research and design of multi-port register file under sub-threshold voltage. In this paper, the design of register file is deeply studied under the TSMC65nm CMOS LP technology, and the 32x32b size register file with 4 read ports and 2 write ports is designed and implemented. In this paper, a register file output module is proposed, which can reduce the power consumption and enhance the robustness. The chip test results show that this version of the register file can work very stably. At 1.2V, the power consumption is only 7.2 MW. At the same time, a register file with sensitive amplifier structure is designed, and a structure that can change the reading line swing is proposed. Secondly, this paper deeply studies and designs a register file with an area of 0.01mm2 only by using a smaller memory cell and a clock pulse control word line. The chip test results show that under the condition of 1.2 V, the working frequency of the chip is 1.56GHz, and the power consumption of register file is 11.8 MW. If the establishment time is not taken into account, the maximum operating frequency of the register file at 1.2 V is about 2 GHz. At the end of this paper, the register file under sub-threshold voltage is studied and designed. First, the working state of CMOS under sub-threshold voltage is analyzed, then based on the working state of CMOS circuit under sub-threshold voltage, a new memory cell is proposed, and a multi-port register file is designed by using a completely different reading and writing method than before.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.11
本文编号：2269806
[Abstract]:With the development of technology, the speed of processor is speeding up. The design methods such as pipeline, superscalar and ultra-long instruction word make the processor more and more complex. These changes put forward higher requirements to register file. The register file needs not only high performance and low power consumption, but also multi-port reading and writing ability. Moreover, with the progress of process, the effect of process fluctuation is becoming more and more serious, especially for register file, which determines the processor performance, so the register file is required to be robust at the same time. In addition, due to the development of medicine and wireless sensor, it is required that the processor can work at lower voltage to greatly reduce power consumption, so the design of low voltage register file has become an important research topic. This paper focuses on the design of high performance, low power, multi-port register file, and the research and design of multi-port register file under sub-threshold voltage. In this paper, the design of register file is deeply studied under the TSMC65nm CMOS LP technology, and the 32x32b size register file with 4 read ports and 2 write ports is designed and implemented. In this paper, a register file output module is proposed, which can reduce the power consumption and enhance the robustness. The chip test results show that this version of the register file can work very stably. At 1.2V, the power consumption is only 7.2 MW. At the same time, a register file with sensitive amplifier structure is designed, and a structure that can change the reading line swing is proposed. Secondly, this paper deeply studies and designs a register file with an area of 0.01mm2 only by using a smaller memory cell and a clock pulse control word line. The chip test results show that under the condition of 1.2 V, the working frequency of the chip is 1.56GHz, and the power consumption of register file is 11.8 MW. If the establishment time is not taken into account, the maximum operating frequency of the register file at 1.2 V is about 2 GHz. At the end of this paper, the register file under sub-threshold voltage is studied and designed. First, the working state of CMOS under sub-threshold voltage is analyzed, then based on the working state of CMOS circuit under sub-threshold voltage, a new memory cell is proposed, and a multi-port register file is designed by using a completely different reading and writing method than before.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.11
【参考文献】
相关硕士学位论文 前4条
1 李毅;高性能低功耗SoC设计以及寄存器堆的应用[D];复旦大学;2011年
2 董方元;寄存器文件的可测性设计与实现[D];复旦大学;2011年
3 张能;600MHz多端口寄存器文件的设计与实现[D];国防科学技术大学;2008年
4 熊保玉;高性能低功耗多端口寄存器文件研究与全定制实现[D];复旦大学;2011年
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