片上多核系统高速缓存的功耗管控方法研究

发布时间：2018-10-15 15:19

【摘要】：随着集成电路工艺的进步以及计算机技术的不断发展,片上多核处理器正逐步取代传统的单核处理器成为未来的主流。然而由于芯片集成度的提高,芯片的功耗密度也越来越大,功耗问题已经成为制约高性能处理器进一步发展的瓶颈。而cache作为连接cpu以及主存之间的缓冲区,其在系统的数据传输及存储中发挥着重要作用。而且由于cache面积的不断增加,其在片上多核系统中所占的功耗比例也越来越大。因此降低cache的功耗对于优化整个片上多核系统的功耗有着至关重要的作用。本文从程序的访存特性入手来优化片上缓存的功耗问题。在程序运行的过程中,通过统计发现可以将缓存的访问分为协议访问和数据访问两种类型,而且其中协议访问占据了几乎一半的访问空间。因此,我们提出了一种软硬件协同的缓存功耗管控方案。该方案是基于现有管控方案中电压门控技术和缓存衰退机制之上改进的一种管控方案,该方案可以在满足程序性能约束的前提下,极大程度上降低系统的功耗。另一方面,在程序运行的过程中,通过跟踪线程的访存行为发现有些线程私有的数据被映射到了离线程较远的地址空间上。该访问特性导致了访问延时的增加以及网络拥塞所引起的网络功耗的增加。因此本文提出了一种线程私有数据地址空间重映射的算法,在一定程度上实现了系统的性能及功耗的双重优化。最后,为了验证本文功耗管控方案的有效性,本文通过软件仿真器对该方案进行了仿真验证,同时也和现有的其他方案进行了对比。仿真结果表明,本文提出的方案可以在对系统造成低于3%的性能损失条件下,降低系统平均75%的功耗。此外,对多线程技术的优化运用到该方案上可以进一步降低系统约3%的网络功耗以及1%的性能损失。
[Abstract]:With the progress of integrated circuit technology and the development of computer technology, the multi-core processor on chip is gradually replacing the traditional single-core processor as the mainstream of the future. However, due to the increase of chip integration, the power density of the chip is also increasing, power consumption has become a bottleneck restricting the further development of high-performance processors. As a buffer between cpu and main memory, cache plays an important role in data transmission and storage. Moreover, with the increasing of cache area, the power consumption of cache in the on-chip multicore system is increasing. Therefore, reducing the power consumption of cache plays an important role in optimizing the power consumption of the whole on-chip multi-core system. In this paper, the memory access characteristics of the program to optimize the power consumption of on-chip cache. In the process of program running, the cached access can be divided into two types: protocol access and data access, and protocol access occupies almost half of the access space. Therefore, we propose a cache power management scheme based on hardware and software co-operation. This scheme is an improved control scheme based on the voltage gating technology and the buffer degradation mechanism in the existing control schemes. The scheme can greatly reduce the power consumption of the system on the premise of satisfying the program performance constraints. On the other hand, in the process of running the program, it is found that some thread-private data are mapped to the address space far away from the thread by tracking the memory access behavior of the thread. This access characteristic leads to the increase of access delay and the increase of network power consumption caused by network congestion. Therefore, this paper proposes an algorithm of thread private data address space remapping, which can optimize the performance and power consumption of the system to a certain extent. Finally, in order to verify the effectiveness of the proposed power management scheme, this paper simulates the scheme by software simulator, and compares it with other existing schemes. The simulation results show that the proposed scheme can reduce the average power consumption of the system by 75% under the condition that the performance loss is less than 3%. In addition, the application of multi-thread technology to the scheme can further reduce the network power consumption of the system by about 3% and the performance loss of 1%.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP332

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