基于FPGA的PCIE总线接口和光纤通信模块设计

发布时间：2018-10-16 18:40

【摘要】：随着计算机性能的不断提高，CPU的时钟频率以及计算机外围接口的带宽成指数地增长，这导致处理器的数据吞吐量也相应的增加。作为第二代总线标准代表的PCI和PCI-X总线，其局限性越来越明显，尤其在带宽和扩展性方面，已经不能满足系统日益增长的需求。PCI Express总线应运而生，，其先进的系统架构、灵活的扩展性和超高的带宽，使得PCI Express迅速适应高速及实时性要求比较高场合，并且会在未来几年内成为总线领域的佼佼者。本课题的主要成果是设计了一种实现PCI Express总线接口和光纤通信模块的硬件系统。该系统以一片高性能的Virtex-6FPGA为核心，物理结构依据PCI Express2.0标准设计，PCI Express总线最多可以扩展到8个通道，理论可支持的最大带宽为40Gbps。同时，系统对外提供可替换的IO接口模块，通过接插光纤模块可以实现主机与外设之间的高速数据传输。首先，对包括PCI Express总线在内的三代总线标准的性能指标进行了对比，归结出PCI Express总线的技术优势，并预测了其未来的发展趋势。对PCI Express总线标准的系统架构、层次结构、事务机制以及配置空间进行了详细的分析，并总结了课题研究时涉及到的关键技术和知识点。然后，详细论述了FPGA系统的硬件设计方案和逻辑设计方案。前者主要包括对系统硬件的总体方案设计和板卡级设计；后者对于系统逻辑设计中比较核心的模块，如PCI Express的DMA数据传输方式、基于Aurora协议的光纤通信方式等，进行了细致的分析，并在文中给出了时序转换图和Verilog代码。最后，用Modelsim和Chipscope工具对设计方案进行了时序仿真和验证，以保证设计的合理性和正确性。通过验证结果可以证明上述方案是可行的。
[Abstract]:With the continuous improvement of computer performance, the clock frequency of CPU and the bandwidth of computer peripheral interface increase exponentially, which leads to the corresponding increase in data throughput of the processor. The limitation of PCI and PCI-X bus, which is the representative of the second generation bus standard, is becoming more and more obvious. Especially in the aspect of bandwidth and expansibility, the. PCI Express bus has been unable to meet the increasing demand of the system, and its advanced system architecture has come into being. Flexible expansibility and ultra-high bandwidth enable PCI Express to adapt to high speed and real-time requirements rapidly and will become the best in the field of bus in the next few years. The main achievement of this thesis is to design a hardware system to realize PCI Express bus interface and optical fiber communication module. The system is based on a high-performance Virtex-6FPGA. The physical structure of the system is designed according to the PCI Express2.0 standard. The, PCI Express bus can be extended to 8 channels at most, and the maximum bandwidth supported by the theory is 40Gbps. At the same time, the system provides the replaceable IO interface module, which can realize the high-speed data transmission between the host computer and the peripheral device by plugging in the optical fiber module. Firstly, the performance indexes of three generation bus standards, including PCI Express bus, are compared, the technical advantages of PCI Express bus are summed up, and the future development trend of PCI Express bus is predicted. The system architecture, hierarchy, transaction mechanism and configuration space of PCI Express bus standard are analyzed in detail, and the key technologies and knowledge points involved in the research are summarized. Then, the hardware design and logic design of FPGA system are discussed in detail. The former mainly includes the overall scheme design of the system hardware and the board level design, while the latter includes the core modules in the system logic design, such as the DMA data transmission mode of PCI Express, the optical fiber communication mode based on the Aurora protocol, etc. Detailed analysis is carried out, and the timing conversion diagram and Verilog code are given in this paper. Finally, the design scheme is simulated and verified with Modelsim and Chipscope tools to ensure the rationality and correctness of the design. The experimental results show that the proposed scheme is feasible.
【学位授予单位】：燕山大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336

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