64位RISC流核心主流水线的设计及优化
发布时间：2018-10-17 07:47
【摘要】：在多核处理器和流处理器的发展都受到限制时，CPU和GPU的异构结构在超级计算机领域创造了性能神话。可是异构体系结构在功耗和数据存储上存在先天性不足，成为其性能瓶颈。因此，CPU和GPU的同构系统渐渐受到业界重视，即同构通用流处理器。 同构通用流处理器是发挥CPU控制能力和GPU数据处理能力的融合产品，其流核心应在满足强大计算性能的同时具有一定的控制能力和可编程能力。根据这一原则，本文基于Microblaze的RISC指令集设计64位流水线并进行优化。为满足同构通用流处理器的性能要求，，所做的工作包括： 1.基于Microblaze的32位指令集，设计64位流水线，对数据结构进行64位扩展，以适应流处理器的运算精度要求以及寻址空间的扩展需要； 2.在细致分析分支指令执行特征的基础上，对流水线添加基于历史信息的分支预测功能，以改善循环和嵌套执行的条件跳转类分支指令的执行效率。另外，分支预测功能可基本消除无条件跳转类分支的执行开销； 3.修改流水线控制信号，在浮点部件中添加流水控制逻辑，让除浮点除和浮点开方指令的其余浮点指令可以流水化执行。浮点流水的设计原则是指令的顺序执行。 论文在Xilinx公司的仿真软件Isim上对流水线进行了全面的功能验证，综合资源利用率情况对其进行性能比较。测试激励本着穷尽原则编写。仿真结果显示设计实现了预期的功能要求。
[Abstract]:At a time when the development of multi-core processors and stream processors is limited, the heterogeneous structures of CPU and GPU create a performance myth in the field of supercomputers. However, there are inherent deficiencies in power consumption and data storage in heterogeneous architecture, which is the bottleneck of its performance. Therefore, the isomorphism system of CPU and GPU has been paid more and more attention, that is, isomorphic universal stream processor. The isomorphic general stream processor is a fusion product which exerts the CPU control ability and the GPU data processing ability. Its stream core should have certain control ability and programmable ability while satisfying the powerful computing performance. According to this principle, this paper designs and optimizes 64 bit pipeline based on RISC instruction set of Microblaze. In order to meet the performance requirements of the isomorphic universal stream processor, the work done includes: 1. Based on 32-bit instruction set of Microblaze, 64-bit pipeline is designed to extend the data structure in order to meet the demand of computational precision and addressable space expansion of flow processor. 2. Based on the detailed analysis of the execution characteristics of branch instructions, a branch prediction function based on historical information is added to the pipeline to improve the execution efficiency of conditional jump branch instructions for loop and nested execution. In addition, the branch prediction function can basically eliminate the execution overhead of the unconditional jump class branch; 3. The pipeline control signal is modified and the pipeline control logic is added to the floating-point component so that the other floating-point instructions except the floating-point except for floating-point and floating-point opening instructions can be pipelined. The design principle of floating-point pipelining is the sequential execution of instructions. In this paper, the function of pipeline is verified on the simulation software Isim of Xilinx Company, and the performance of pipeline is compared by comprehensive resource utilization. Test incentives are written on an exhaustive basis. Simulation results show that the design achieves the expected functional requirements.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
本文编号：2275998
[Abstract]:At a time when the development of multi-core processors and stream processors is limited, the heterogeneous structures of CPU and GPU create a performance myth in the field of supercomputers. However, there are inherent deficiencies in power consumption and data storage in heterogeneous architecture, which is the bottleneck of its performance. Therefore, the isomorphism system of CPU and GPU has been paid more and more attention, that is, isomorphic universal stream processor. The isomorphic general stream processor is a fusion product which exerts the CPU control ability and the GPU data processing ability. Its stream core should have certain control ability and programmable ability while satisfying the powerful computing performance. According to this principle, this paper designs and optimizes 64 bit pipeline based on RISC instruction set of Microblaze. In order to meet the performance requirements of the isomorphic universal stream processor, the work done includes: 1. Based on 32-bit instruction set of Microblaze, 64-bit pipeline is designed to extend the data structure in order to meet the demand of computational precision and addressable space expansion of flow processor. 2. Based on the detailed analysis of the execution characteristics of branch instructions, a branch prediction function based on historical information is added to the pipeline to improve the execution efficiency of conditional jump branch instructions for loop and nested execution. In addition, the branch prediction function can basically eliminate the execution overhead of the unconditional jump class branch; 3. The pipeline control signal is modified and the pipeline control logic is added to the floating-point component so that the other floating-point instructions except the floating-point except for floating-point and floating-point opening instructions can be pipelined. The design principle of floating-point pipelining is the sequential execution of instructions. In this paper, the function of pipeline is verified on the simulation software Isim of Xilinx Company, and the performance of pipeline is compared by comprehensive resource utilization. Test incentives are written on an exhaustive basis. Simulation results show that the design achieves the expected functional requirements.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
【参考文献】
相关期刊论文 前2条
1 黄伟;王玉艳;章建雄;;嵌入式处理器动态分支预测机制研究与设计[J];计算机工程;2008年21期
2 陈弦;于伦正;;运算流水线的实现和优化[J];微电子学与计算机;2006年01期
本文编号：2275998
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