高性能硬件加速器的实现

发布时间：2018-10-18 20:32

【摘要】：在现代复杂数字信号处理中,随着算法复杂度和待处理数据量的日益剧增,通用处理器已经难以满足某些特定应用中数据处理的高速实时性要求。异构多核系统可以将不同的计算任务分配到不同的处理器核进行并行处理,加速任务执行,提供了更加高效、灵活的处理机制,满足多种应用的需求。硬件加速器可提高面向特定应用中科学计算的运算速度。因此,集成有硬件加速器形式的异构多核系统架构应运而生。一些多核处理器通过集成专用的加速器核对某些特定应用进行加速运算,但是其灵活性不高。随着可重构技术的出现,将可重构技术应用于硬件加速器中,能够弥补通用运算和软件计算在性能和灵活性上的不足,为复杂高速信号的处理提出了更好的解决方案。本文根据发展趋势,对可重构计算技术、硬件加速器,以及如何在异构多核系统中集成硬件加速器进行了研究。本文主要从以下三个方面进行了研究:(1)根据应用目标需求特征,分析面向高密度计算的应用特点,并对矩阵算法特征进行研究分析,分析出并行程度高、可有效提高系统性能的矩阵计算方法,并针对应用目标和应用平台对矩阵运算类型的算法进行了优化,得到了原位替换的混合粒度并行矩阵求逆实现方法。(2)在优化算法和结构的基础上,提出了优化后的矩阵求逆算法的硬件架构,设计了面向异构多核系统的可重构高性能硬件加速器。该硬件加速器主要面向高密度计算领域中矩阵类运算。特别是矩阵求逆运算,能够高效地完成128阶以内2n阶单精度任意浮点实数矩阵的求逆运算。(3)基于Xilinx V6 FPGA对设计的硬件加速器进行了实验验证和性能分析,并介绍了该硬件加速器在异构多核系统中的集成,验证了所设计的硬件加速器具有较高的性能。
[Abstract]:In modern complex digital signal processing, with the increasing complexity of the algorithm and the amount of data to be processed, the general-purpose processor has been unable to meet the requirements of high-speed real-time data processing in some specific applications. Heterogeneous multi-core systems can assign different computing tasks to different processor cores for parallel processing, accelerate task execution, provide a more efficient and flexible processing mechanism, and meet the needs of various applications. Hardware accelerators can improve the speed of scientific computation for specific applications. Therefore, the architecture of heterogeneous multicore system with hardware accelerator has emerged as the times require. Some multicore processors perform accelerated operations by integrating specialized accelerators for certain applications, but their flexibility is not high. With the advent of reconfigurable technology, the application of reconfigurable technology to hardware accelerators can make up for the shortcomings of performance and flexibility in general computing and software computing, and provide a better solution for complex high-speed signal processing. According to the development trend, this paper studies reconfigurable computing technology, hardware accelerator and how to integrate hardware accelerator in heterogeneous multi-core system. In this paper, the following three aspects are studied: (1) according to the requirements of the application target, the application characteristics of high-density computing are analyzed, and the characteristics of matrix algorithm are analyzed, and the high degree of parallelism is analyzed. The matrix calculation method which can improve the system performance effectively, and the algorithm of matrix operation type is optimized according to the application target and application platform. A hybrid granularity parallel matrix inversion method with in-situ substitution is obtained. (2) based on the optimization algorithm and structure, the hardware architecture of the optimized matrix inversion algorithm is proposed. A reconfigurable high performance hardware accelerator for heterogeneous multi-core systems is designed. The hardware accelerator is mainly used for matrix operations in the field of high density computing. Especially, the inverse operation of matrix can efficiently perform the inversion of real matrix with single precision of 2n within order 128. (3) based on Xilinx V6 FPGA, the experimental verification and performance analysis of the designed hardware accelerator are carried out. The integration of the hardware accelerator in heterogeneous multicore system is introduced, and the high performance of the designed accelerator is verified.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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