基于Stratix Ⅳ FPGA双DDR2接口的信号完整性与时序分析

发布时间：2018-10-25 18:57

【摘要】：众所周知,在PCB版图设计中,MCU与DDR2间的走线排布是件非常困难的事情。而在实际应用中,含有双DDR2的设计尤为常见。本论文既以Altera公司的Stratix IV FPGA与Micron公司的MT47H18M8DDR2接口数据通信为研究对象,通过分析DDR2接口的数字电平形态与时序,制订一个PCB排布方案,使得CPU与DDR2之间的通信更为可靠。论文分别深入分析了所有类型DDR2接口的信号,包括时钟信号、地址/命令信号、写数据选通信号以及写数据信号。通过PCB传输线的阻抗控制、传输线T型分枝结构的优化、驱动电流的选取以及最重要的端接或片上终结电阻,来实现数字波形的修饰与幅度调整,从而获得最优的电平判决。另一方面,在时钟系统中由于双DDR2接口的地址/命令捕获与时钟信号构成源同步时钟系统,写数据捕获与写数据选通信号也构成源同步时钟系统。但二者的区别在于,写数据捕获是在选通信号的上下沿触发,而地址/命令捕获只在时钟信号的上跳沿触发。在各自的源同步时钟系统中,同时使建立时间裕量与保持时间裕量最大,即建立时间裕量等于保持时间裕量。本论文通过找出系统的建立/保持时间裕量与时钟线、选通线、数据线以及地址/命令线信号传输时延的关系,进一步结合阻抗控制下的单位长度PCB传输线的时延,得到建立/保持时间裕量与PCB传输线长度的关系。通过调整传输线的长度,来实现建立时间与保持时间裕量的最大。论文中对时序的仿真,使用了眼图测量与眼图模板标示。首先分别设定数据线、数据选通线、地址/命令线以及时钟线的长度。通过建立电路模型并输出眼图,制作眼图模板。在眼图模板上显示出建立时间、保持时间、建立时间裕量、保持时间裕量以及时钟抖动。这样可以直观的显示出需要调整的时间裕量,以方便通过走线长度的调整实现时间裕量的调整。
[Abstract]:As we all know, the routing between MCU and DDR2 is very difficult in PCB layout design. In practical application, the design with double DDR2 is particularly common. In this paper, the data communication between Stratix IV FPGA of Altera Company and MT47H18M8DDR2 of Micron Company is taken as the research object. By analyzing the digital level configuration and timing of DDR2 interface, an arrangement scheme of PCB is developed, which makes the communication between CPU and DDR2 more reliable. This paper analyzes the signals of all kinds of DDR2 interface, including clock signal, address / command signal, write data strobe signal and write data signal. Through the impedance control of the PCB transmission line, the optimization of the T-type branch structure of the transmission line, the selection of the driving current and the most important terminal or on-chip end resistor, the modification and amplitude adjustment of the digital waveform are realized, and the optimal level decision is obtained. On the other hand, in the clock system, because the address / command acquisition and clock signal of dual DDR2 interface constitute the source synchronous clock system, the write data capture and write data strobe signal also constitute the source synchronous clock system. However, the difference between them is that the write data capture is triggered at the upper and lower edge of the strobe signal, while the address / command capture only triggers the hopping edge of the clock signal. In their respective source synchronous clock systems, the establishment time margin and the hold time margin are maximized at the same time, that is, the establishment time margin is equal to the hold time margin. In this paper, we find out the relationship between the establishment / retention time margin of the system and the transmission delay of clock line, strobe line, data line and address / command line, and further combine the delay of unit length PCB transmission line under impedance control. The relationship between the establishment / retention time margin and the length of PCB transmission line is obtained. By adjusting the length of transmission line, the maximum amount of time margin is realized. In this paper, the timing of the simulation, the use of eye chart measurement and eye chart template marking. First, set the length of the data line, the data strobe line, the address / command line and the clock line respectively. By establishing the circuit model and outputting the eye diagram, the eye diagram template is made. The setup time, hold time, build time margin, hold time margin and clock jitter are displayed on the eye chart template. In this way, the time margin needed to be adjusted can be displayed intuitively, so that the adjustment of time margin can be realized easily through the adjustment of line length.
【学位授予单位】：华中师范大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7;TN791

【共引文献】