一种容错可逆的通用移位寄存器设计
发布时间：2018-10-29 22:37
【摘要】：为了使计算系统具有低功耗和容错能力,基于可逆逻辑设计了一种容错的通用移位寄存器。提出了一种新型的容错可逆逻辑门(Parity-preserving D flip_flop gate,PP_DFG),利用它和存在的容错门,完成了寄存器和多路数据选择器的设计。综合上述模块,构建了容错可逆的通用移位寄存器电路,用Verilog硬件描述语言建模,仿真显示电路逻辑结构正确。同现有电路相比,根据量子代价、延迟和无用输出对其进行性能评估,结果表明该电路不仅具有容错功能,而且性能提高了16%~48%。设计的电路可作为一种重要的存储元件应用于未来的低功耗计算系统。
[Abstract]:In order to make the computing system have low power consumption and fault-tolerant capability, a fault-tolerant general shift register is designed based on reversible logic. A novel fault-tolerant reversible logic gate (Parity-preserving D flip_flop gate,PP_DFG) is proposed. Using it and the existing fault-tolerant gate, the register and multiplexer are designed. A fault-tolerant and reversible universal shift register circuit is constructed by synthesizing the above modules. The Verilog hardware description language is used to model the model and the simulation results show that the logic structure of the circuit is correct. Compared with the existing circuit, the performance of the circuit is evaluated according to quantum cost, delay and useless output. The results show that the circuit not only has fault-tolerant function, but also improves its performance by 16 / 48. The designed circuit can be used as an important memory element in the future low-power computing system.
【作者单位】： 安徽师范大学数学计算机科学学院;安徽师范大学网络与信息安全工程技术研究中心;
【基金】：国家自然科学基金项目(61370050) 安徽省自然科学基金项目(1308085QF118) 安徽省高校省级自然科学研究项目重点项目(KJ2014A084) 安徽师范大学创新基金项目(2013CXJJ01)资助
【分类号】：TP332.11
本文编号：2299036
[Abstract]:In order to make the computing system have low power consumption and fault-tolerant capability, a fault-tolerant general shift register is designed based on reversible logic. A novel fault-tolerant reversible logic gate (Parity-preserving D flip_flop gate,PP_DFG) is proposed. Using it and the existing fault-tolerant gate, the register and multiplexer are designed. A fault-tolerant and reversible universal shift register circuit is constructed by synthesizing the above modules. The Verilog hardware description language is used to model the model and the simulation results show that the logic structure of the circuit is correct. Compared with the existing circuit, the performance of the circuit is evaluated according to quantum cost, delay and useless output. The results show that the circuit not only has fault-tolerant function, but also improves its performance by 16 / 48. The designed circuit can be used as an important memory element in the future low-power computing system.
【作者单位】： 安徽师范大学数学计算机科学学院;安徽师范大学网络与信息安全工程技术研究中心;
【基金】：国家自然科学基金项目(61370050) 安徽省自然科学基金项目(1308085QF118) 安徽省高校省级自然科学研究项目重点项目(KJ2014A084) 安徽师范大学创新基金项目(2013CXJJ01)资助
【分类号】：TP332.11
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