基于SystemVerilog的向量存储器验证方法
发布时间：2018-11-02 15:45
【摘要】：随着半导体工艺的发展,片上存储器的设计容量和复杂度日益增长,传统的功能验证方法面临着验证完备性、可重用性、效率和可靠性等方面挑战.针对自主设计的某16路SIMD结构的大容量向量存储器(vector memory,VM)覆盖率驱动的验证方法进行研究,基于SystemVerilog验证方法学,采用层次化建模方法搭建了高效的VM验证平台,在较高抽象层次上实现了带约束的随机激励,结合SVA断言技术对向量存储器向量读访存流水线的同步与提交状态实时监控,保证了关键时序逻辑功能验证的完备性、正确性,有效提高了验证效率.最终模块级验证结果表明,定向激励和随机激励相结合能较快达到理想的代码覆盖率.
[Abstract]:With the development of semiconductor technology, the design capacity and complexity of on-chip memory are increasing day by day. Traditional functional verification methods face challenges of completeness, reusability, efficiency and reliability. In this paper, a self-designed verification method for a 16-channel SIMD structure with mass capacity vector memory (vector memory,VM) coverage driven is studied. Based on the SystemVerilog verification methodology, an efficient VM verification platform is built by using hierarchical modeling method. At a higher level of abstraction, the constrained random excitation is realized, and the synchronization and submission state of vector memory read and access pipeline is monitored in real time with SVA assertion technology, which ensures the completeness and correctness of the verification of key temporal logic functions. The efficiency of verification is improved effectively. The final modular level verification results show that the combination of directional excitation and random excitation can achieve an ideal code coverage quickly.
【作者单位】： 国防科学技术大学计算机学院;
【基金】：国家自然科学基金项目(61303065) 国防科学技术大学科研计划基金项目(JC13-06-02) 教育部高等学校博士学科点专项科研基金项目(20134307120028)
【分类号】：TP333
本文编号：2306225
[Abstract]:With the development of semiconductor technology, the design capacity and complexity of on-chip memory are increasing day by day. Traditional functional verification methods face challenges of completeness, reusability, efficiency and reliability. In this paper, a self-designed verification method for a 16-channel SIMD structure with mass capacity vector memory (vector memory,VM) coverage driven is studied. Based on the SystemVerilog verification methodology, an efficient VM verification platform is built by using hierarchical modeling method. At a higher level of abstraction, the constrained random excitation is realized, and the synchronization and submission state of vector memory read and access pipeline is monitored in real time with SVA assertion technology, which ensures the completeness and correctness of the verification of key temporal logic functions. The efficiency of verification is improved effectively. The final modular level verification results show that the combination of directional excitation and random excitation can achieve an ideal code coverage quickly.
【作者单位】： 国防科学技术大学计算机学院;
【基金】：国家自然科学基金项目(61303065) 国防科学技术大学科研计划基金项目(JC13-06-02) 教育部高等学校博士学科点专项科研基金项目(20134307120028)
【分类号】：TP333
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