任意点存储器结构FFT处理器地址策略
发布时间：2018-11-07 16:54
【摘要】：提出一种针对任意点数运算的并行地址无冲突的存储器结构的FFT处理器.该方法利用高基底的分解方法减少整体计算时钟周期,以及小基底互联的多路延迟交换结构降低计算引擎的复杂度.该方法可以将存储器结构FFT处理器中的几个重要特性如连续帧处理模式,多点数计算和并行无地址冲突等特点集成在一起.另外,素因子FFT算法也被运用到该处理器当中用以降低乘法器个数和蝶形因子存储,以及满足任意点数的计算需求.设计了一种统一的基-2,3,4,5的Winograd算法的蝶形计算单元用以降低计算复杂度.实验仿真结果表明,本FFT处理器在122.88MHz工作频率下功耗只有40.8mW,非常适合LTE系统的应用.
[Abstract]:This paper presents a memory architecture FFT processor for any number of parallel addresses. In this method, the decomposition method of high substrate is used to reduce the overall computing clock cycle and the complexity of the computing engine is reduced by the multi-channel delay switching structure of the small substrate interconnection. This method can integrate several important features of memory architecture FFT processor, such as continuous frame processing mode, multi-point computation and parallel address-free collision. In addition, the prime factor FFT algorithm is also applied to the processor to reduce the number of multipliers and the storage of butterfly factors, and to meet the calculation requirements of arbitrary points. In this paper, a butterfly computing unit of a unified base-2 / 3 / 4 / 5 Winograd algorithm is designed to reduce the computational complexity. The simulation results show that the power consumption of the FFT processor is only 40.8 MW at the 122.88MHz operating frequency, which is very suitable for the application of LTE system.
【作者单位】： 中国科学院微电子研究所;
【分类号】：TP332;TP333
本文编号：2316970
[Abstract]:This paper presents a memory architecture FFT processor for any number of parallel addresses. In this method, the decomposition method of high substrate is used to reduce the overall computing clock cycle and the complexity of the computing engine is reduced by the multi-channel delay switching structure of the small substrate interconnection. This method can integrate several important features of memory architecture FFT processor, such as continuous frame processing mode, multi-point computation and parallel address-free collision. In addition, the prime factor FFT algorithm is also applied to the processor to reduce the number of multipliers and the storage of butterfly factors, and to meet the calculation requirements of arbitrary points. In this paper, a butterfly computing unit of a unified base-2 / 3 / 4 / 5 Winograd algorithm is designed to reduce the computational complexity. The simulation results show that the power consumption of the FFT processor is only 40.8 MW at the 122.88MHz operating frequency, which is very suitable for the application of LTE system.
【作者单位】： 中国科学院微电子研究所;
【分类号】：TP332;TP333
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