微处理器电快速瞬变脉冲群测试方法与防护技术研究
发布时间：2018-11-08 09:01
【摘要】：作为现代电子系统的核心，微处理器往往在电子系统的电磁兼容中扮演着重要角色。随着集成电路制造工艺的不断进步，特征尺寸的不断减小，微处理器的工作频率和集成度越来越高、工作电压越来越低，，对外界电磁干扰越来越敏感。出于系统设计人员对集成电路电磁兼容性的要求，迫切的需要研究微处理器电快速瞬变脉冲群（EFT）测试方法来衡量微处理器对EFT干扰的抗扰度性能，并开展相应的微处理器片上EFT防护设计研究以提高微处理器的EFT抗扰度。本文正是针对这种需求，在分析系统级EFT测试方法和总结现有集成电路瞬态抗扰度测试方案的基础上，实现了一种微处理器EFT测试方法，并对相应的微处理器片上EFT防护设计的Trigger电路展开了研究。 第一部分实现了一种微处理器EFT测试方法。首先对系统级EFT测试方法展开研究，分析了系统级EFT干扰对微处理器的危害及其作用机理。然后对目前集成电路级瞬态脉冲抗扰度测试的几种可行方案进行分析与对比。最后确定了本文所采用的方案，从测试环境设置、测试硬件设计、测试软件设计以及测试流程等几方面进行了详细论述。 第二部分通过测试案例对测试方法的性能展开研究。主要选取了一款微处理器芯片进行了实际测试，通过对测试案例结果的分析，总结了测试过程中发现的问题，对微处理器EFT测试过程中出现的几种失效模式及机理进行了相应的研究，并通过实验对测试结果的重复性和重现性问题进行了深入研究。 第三部分对微处理器片上EFT防护设计的Trigger电路展开了研究。根据对EFT防护电路性能要求的分析，结合微处理器片上ESD防护电路结构，提出了一种EFT Trigger电路，利用片上ESD保护电路实现对EFT干扰的防护，并通过仿真分析以及实际测试对该防护电路的性能进行了验证。
[Abstract]:As the core of modern electronic system, microprocessor often plays an important role in electromagnetic compatibility of electronic system. With the development of integrated circuit manufacturing technology and the decrease of characteristic size, the working frequency and integration of microprocessors are higher and higher, the working voltage is lower and lower, and they are more sensitive to external electromagnetic interference (EMI). In order to meet the requirements of the system designers for the electromagnetic compatibility of integrated circuits, it is urgent to study the (EFT) test method of the microprocessor electric fast transient pulse group to measure the immunity of the microprocessor to EFT interference. In order to improve the EFT immunity of microprocessor, the corresponding design of EFT protection on chip is carried out. In this paper, a microprocessor EFT testing method is implemented on the basis of analyzing system-level EFT test methods and summarizing the existing IC transient immunity test schemes. The Trigger circuit designed for EFT protection is studied. In the first part, a microprocessor EFT testing method is implemented. Firstly, the system-level EFT testing method is studied, and the harm of system-level EFT interference to microprocessor and its mechanism are analyzed. Then several feasible schemes of IC transient pulse immunity test are analyzed and compared. Finally, the scheme of this paper is determined, including the setting of test environment, the design of test hardware, the design of test software and the test flow. In the second part, the performance of the test method is studied through test cases. A microprocessor chip is selected for practical test. Through the analysis of test cases, the problems found in the testing process are summarized. Several failure modes and mechanisms in the process of microprocessor EFT testing are studied, and the repeatability and reproducibility of the test results are studied through experiments. In the third part, the Trigger circuit designed for EFT protection on microprocessor chip is studied. Based on the analysis of the performance requirements of EFT protection circuit and combined with the structure of ESD protection circuit on microprocessor chip, a EFT Trigger circuit is proposed to protect EFT from interference by using on-chip ESD protection circuit. The performance of the protective circuit is verified by simulation analysis and actual test.
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP332
本文编号：2318003
[Abstract]:As the core of modern electronic system, microprocessor often plays an important role in electromagnetic compatibility of electronic system. With the development of integrated circuit manufacturing technology and the decrease of characteristic size, the working frequency and integration of microprocessors are higher and higher, the working voltage is lower and lower, and they are more sensitive to external electromagnetic interference (EMI). In order to meet the requirements of the system designers for the electromagnetic compatibility of integrated circuits, it is urgent to study the (EFT) test method of the microprocessor electric fast transient pulse group to measure the immunity of the microprocessor to EFT interference. In order to improve the EFT immunity of microprocessor, the corresponding design of EFT protection on chip is carried out. In this paper, a microprocessor EFT testing method is implemented on the basis of analyzing system-level EFT test methods and summarizing the existing IC transient immunity test schemes. The Trigger circuit designed for EFT protection is studied. In the first part, a microprocessor EFT testing method is implemented. Firstly, the system-level EFT testing method is studied, and the harm of system-level EFT interference to microprocessor and its mechanism are analyzed. Then several feasible schemes of IC transient pulse immunity test are analyzed and compared. Finally, the scheme of this paper is determined, including the setting of test environment, the design of test hardware, the design of test software and the test flow. In the second part, the performance of the test method is studied through test cases. A microprocessor chip is selected for practical test. Through the analysis of test cases, the problems found in the testing process are summarized. Several failure modes and mechanisms in the process of microprocessor EFT testing are studied, and the repeatability and reproducibility of the test results are studied through experiments. In the third part, the Trigger circuit designed for EFT protection on microprocessor chip is studied. Based on the analysis of the performance requirements of EFT protection circuit and combined with the structure of ESD protection circuit on microprocessor chip, a EFT Trigger circuit is proposed to protect EFT from interference by using on-chip ESD protection circuit. The performance of the protective circuit is verified by simulation analysis and actual test.
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP332
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