基于状态机的PLC处理器设计研究

发布时间：2018-11-10 07:44

【摘要】：随着PLC应用的迅速发展,PLC对处理器的要求也随之不断提高。PLC需要处理器像商用处理器那样越来越廉价,像DSP处理器那样数据处理能力越来越强,特别是需要处理器具备工业应用现场上的实时处理性能。本文对现有PLC及其处理器的发展现状、发展方向、工作方式、工作需求进行了大量的研究和分析,在此基础上,设计了一款针对于PLC应用的实时性高效率的处理器——基于状态机的PLC处理器。经过研究,笔者在本文中提出了高效率处理器理念和状态机群理念,并将状态机群理念作为本论文的创新点。高效率处理器理念就是,以尽量少的程序代码完成尽量多的数据处理,其具体描述指标是MDPS(Millions of Data Per Second,每秒多少百万数据)和DIR(Data Instructions Ratio,数据指令比);状态机群理念就是通过主状态机-从状态机的状态机群来实现较为复杂而重复的具体的数据处理操作(8051单片机的SFR部分,就是CPU控制下的一种可配置状态机群);避免重复取指令造成的总线占用,以获得比RISC更高的数据处理效率,比DSP更高的灵活性;通过数组加法和链表搜索的算例作了具体的详细解释。本文完成了基于状态机的PLC处理器的如下设计:处理器架构设计(操作集成的数组加法和链表搜索);指令系统设计(程序计数器设计、取指令操作设计、指令集设计、指令码设计、特殊功能寄存器设计);并且运用Verilog HDL硬件描述语言编程实现了,主从状态机、状态机群、状态机群的存储器、状态机处理器指令等。其中状态机处理器指令的Verilog实现包括:通用指令的实现、状态机群指令的实现、数组加法及链表搜索的实现、特殊功能的实现。并且利用Modelsim SE软件,结合FPGA技术,对基于状态机的PLC处理器的寻址方式、通用指令、状态机群、定时器、中断、数组加法及链表搜索进行逻辑功能的仿真验证,仿真结果证明了基于状态机的PLC处理器的可行性。
[Abstract]:With the rapid development of PLC applications, the requirements of PLC for processors are increasing. PLC requires processors to be as cheap as commercial processors, and data processing capabilities like DSP processors are becoming stronger and stronger. In particular, the processor is required to have real-time processing performance on the industrial application field. This paper has carried on the massive research and the analysis to the present PLC and its processor development present situation, the development direction, the working way, the work demand, on this basis, A real-time and efficient processor for PLC application is designed, which is based on state machine based PLC processor. Through research, the author puts forward the idea of high efficiency processor and state cluster, and takes the concept of state machine cluster as the innovation of this paper. The idea of an efficient processor is to do as much data processing as possible with as little program code as possible, the specification of which is how many millions of MDPS (Millions of Data Per Second, data per second) and the DIR (Data Instructions Ratio, data instruction ratio). The concept of state cluster is to realize complex and repeated data processing operations through the state cluster of master state machine and slave state machine (the SFR part of 8051 single chip microcomputer is a configurable state cluster under CPU control); In order to obtain higher data processing efficiency than RISC and more flexibility than DSP, the bus footprint caused by repeated fetching instructions is avoided. The examples of array addition and linked list search are explained in detail. In this paper, the state machine based PLC processor is designed as follows: processor architecture design (operation integrated array addition and list search); Instruction system design (program counter design, instruction operation design, instruction set design, instruction code design, special function register design); And the Verilog HDL hardware description language is used to realize the master-slave state machine, the memory of the state machine group, the state machine processor instruction and so on. The Verilog implementation of state machine processor instruction includes the realization of general instruction, the realization of state cluster instruction, the realization of array addition and chain list search, and the realization of special function. Using Modelsim SE software and FPGA technology, the logic function of PLC processor based on state machine, general instruction, state cluster, timer, interrupt, array addition and chain list search are simulated. The simulation results show the feasibility of the state machine based PLC processor.
【学位授予单位】：沈阳理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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