基于FPGA与DSP的多波束相干测深算法的实现

发布时间：2018-11-12 13:05

【摘要】：多波束测深系统在海洋探测和水下工程中起着不可替代的作用。目前大部分多波束测深设备通过对中间波束和边缘波束分别使用幅度检测法和相位差检测法进行测量，这导致了测深值在中间和边缘区域分布不均匀的问题。多波束相干测深算法能够较好的解决传统算法测量分辨率不均的问题，而且能使测深系统的水下目标探测能力得到较大的提高。论文提出一种基于FPGA与DSP硬件平台的多波束相干测深算法实现方案。该方案能够充分结合FPGA与DSP芯片各自的特点，不但节约了系统资源，也使处理速度有效提高，同时使该算法在实际工程中的实时实现问题得到解决。系统的硬件平台FPGA芯片为Altera公司CycloneII系列芯片EP2C50F484C，所实现的功能包括希尔伯特变换器、数据缓冲、子阵划分、补零处理、128点FFT波束形成以及数据上传等功能模块，在此基础上本文对算法进行了优化，进一步降低了毛刺和亚稳态的产生。DSP芯片为TI公司的TMS320C6713B芯片，所实现的功能包括计算相干信号相位差、获取DOA、TOA信息并换算成深度和水平信息等。通过一片FPGA和两片DSP的协同处理，大幅度提高了算法的实现性能。此外，，硬件平台还包含80通道的A/D采集模块，可以更加全面、高效的完成数据的处理过程。本文通过ModelSim时序仿真和Quartus波形仿真验证了FPGA各个功能模块逻辑时序的正确性；将DSP处理数据的关键步骤数据与MATLAB平台的仿真数据进行比较验证和误差分析，可得到处理结果与仿真结果基本一致的结论。因为FPGA的并行性设计、内部流水线技术的使用，以及两块DSP的并行作业，所以算法的运行效率得到了有效的提高。通过算法实现的性能和结果分析，整体设计满足设计要求，达到了预期的效果。
[Abstract]:Multi-beam sounding system plays an irreplaceable role in ocean exploration and underwater engineering. At present, most multi-beam bathymetry equipment use amplitude detection method and phase difference detection method to measure the intermediate beam and edge beam respectively, which leads to the problem of uneven distribution of sounding value in the middle and edge region. Multi-beam coherent sounding algorithm can solve the problem of uneven resolution of traditional algorithms, and can improve the underwater target detection ability of the bathymetric system. This paper presents a multi-beam coherent sounding algorithm based on FPGA and DSP hardware platform. This scheme can fully combine the characteristics of FPGA and DSP chips, which not only saves the system resources, but also improves the processing speed effectively. At the same time, the real-time implementation of the algorithm in practical engineering is solved. The hardware platform FPGA chip of the system is implemented by Altera CycloneII series chip EP2C50F484C, including Hilbert converter, data buffering, subarray partition, zero compensation processing, 128-point FFT beamforming and data uploading, etc. On this basis, the algorithm is optimized to further reduce the burr and metastable state. The DSP chip is a TMS320C6713B chip of TI, the functions of which include calculating the phase difference of coherent signal and obtaining DOA,. TOA information and converted into depth and level information, etc. The performance of the algorithm is greatly improved by the cooperative processing of one FPGA and two pieces of DSP. In addition, the hardware platform also includes 80 channel Ar / D acquisition module, which can complete the data processing more comprehensively and efficiently. In this paper, the correctness of the logic timing of each function module of FPGA is verified by ModelSim time series simulation and Quartus waveform simulation. By comparing the key step data of DSP processing with the simulation data of MATLAB platform, we can get the conclusion that the processing result is basically consistent with the simulation result. Because of the parallelism design of FPGA, the use of internal pipeline technology and the parallel operation of two blocks of DSP, the efficiency of the algorithm has been improved effectively. Through the performance and result analysis of the algorithm, the overall design meets the design requirements and achieves the desired results.
【学位授予单位】：哈尔滨工程大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN911.7;TP368.1

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