基于FPGA的USB3.0物理层数字电路研究与设计
发布时间：2018-11-17 06:48
【摘要】：随着通信行业的飞速发展,数据传输的速度要求也越来越高。原先的480Mbps的USB2.0传输速度已经不能满足数据传输的需求,于是传输速度5Gbps的 USB3.0 应运而生。USB3.0 Promoter Group 是由微软、惠普、Intel、NEC、ST-NXP、德州仪器等IT行业巨头组成的,该组织于2008年宣布制定的新一代USB3.0标准已经顺利完成并且公开发布了。USB3.0无论在传输速度还是在性能方面都有非常大的提升。论文详细介绍了 USB3.0物理层数字电路模块的划分以及相应模块的的原理,功能和详细的电路设计,最后运用Verilog硬件语言编写相应代码,并完成功能仿真。论文研究IEEE指定的USB3.0的详细标准规范,主要针对第六章物理层的相关知识进行学习和研究。并在研究的过程中对数字模块进行电路设计,首先对于物理层和数字链路层数据传输进行分析,然后具体对8B/10B编码器和解码器模块,K28.5检测模块,接收状态检测模块,弹性缓冲器模块进行数字电路设计,最后运用Verilog硬件语言描述,运用QuatursⅡ开发工具进行功能仿真。论文依据USB3.0标准规范,基于FPGA分别按要求实现各个模块的数字电路设计。仿真结果显示基本能够完成目标要求。
[Abstract]:With the rapid development of the communication industry, the speed of data transmission is higher and higher. The USB2.0 transmission speed of the original 480Mbps can no longer meet the demand of data transmission, so the USB3.0 of the transmission speed 5Gbps came into being. USB3.0 Promoter Group is composed of IT giants such as Microsoft, HP, Intel,NEC,ST-NXP, Texas Instruments, etc. The group announced in 2008 that a new generation of USB3.0 standards had been successfully completed and publicly released. USB3.0 has made significant improvements in both speed and performance. The paper introduces the division of the USB3.0 physical layer digital circuit module, the principle of the corresponding module, the function and the detailed circuit design in detail. Finally, the corresponding code is compiled by using the Verilog hardware language, and the functional simulation is completed. This paper studies the detailed standard specification of USB3.0 specified by IEEE, and mainly studies the related knowledge of physical layer in Chapter 6. In the process of research, the circuit design of digital module is carried out. Firstly, the data transmission of physical layer and digital link layer is analyzed, then the 8B/10B encoder and decoder module, K28.5 detection module, receiving status detection module are concretely analyzed. The elastic buffer module is used to design the digital circuit. Finally, the Verilog hardware language is used to describe the function and the Quaturs 鈪，
本文编号：2336830
[Abstract]:With the rapid development of the communication industry, the speed of data transmission is higher and higher. The USB2.0 transmission speed of the original 480Mbps can no longer meet the demand of data transmission, so the USB3.0 of the transmission speed 5Gbps came into being. USB3.0 Promoter Group is composed of IT giants such as Microsoft, HP, Intel,NEC,ST-NXP, Texas Instruments, etc. The group announced in 2008 that a new generation of USB3.0 standards had been successfully completed and publicly released. USB3.0 has made significant improvements in both speed and performance. The paper introduces the division of the USB3.0 physical layer digital circuit module, the principle of the corresponding module, the function and the detailed circuit design in detail. Finally, the corresponding code is compiled by using the Verilog hardware language, and the functional simulation is completed. This paper studies the detailed standard specification of USB3.0 specified by IEEE, and mainly studies the related knowledge of physical layer in Chapter 6. In the process of research, the circuit design of digital module is carried out. Firstly, the data transmission of physical layer and digital link layer is analyzed, then the 8B/10B encoder and decoder module, K28.5 detection module, receiving status detection module are concretely analyzed. The elastic buffer module is used to design the digital circuit. Finally, the Verilog hardware language is used to describe the function and the Quaturs 鈪，
本文编号：2336830
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