基于FPGA的XDNP原型验证平台设计与实现
发布时间：2018-11-18 19:19
【摘要】：XDNP网络处理器是一个单片多处理器系统，内部包含大量用于处理网络协议的硬件模块、多核多线程的调度模块、以及总线仲裁模块等。因此，在对网络处理器功能验证的过程中，基于EDA工具的仿真手段效率低下，，验证时间冗长。而FPGA原型验证通过搭建真实的应用环境来验证芯片设计的正确性，克服了基于仿真器的系统级验证所具有的仿真速度慢、验证不全面等缺点，使得验证工作更加快速和全面。 基于以上目的，本文主要研究内容为XDNP网络处理器的FPGA原型验证平台设计。本文将硬件验证方案分为两种：FPGA原型验证和MPE-BUS芯片验证。在FPGA原型验证方案中，XDNP全部功能由FPGA芯片实现；MPE-BUS芯片验证方案中，本课题组采用eASIC Nextreme90nm工艺将XDNP系统中最核心部分，即6个同构包处理引擎PE及片上总线，进行流片，得到MPE-BUS芯片，剩余功能采用FPGA实现。 本文提出了验证平台的设计方案，完成了XDNP-DEMODOARD板的原理图设计，并实现了该验证平台的硬件设计。利用该验证平台，基于Intel IXP1200系统附带的L3fwd8_1f和L3fwd2f参考程序对XDNP系统完成了功能验证，其中L3fwd8_1f参考程序用于百兆对百兆路由功能的测试，L3fwd2f参考程序用于千兆对千兆路由功能的测试，验证结果表明FPGA原型和MPE-BUS芯片验证方案均能正确实现百兆口和百兆口之间以及千兆口和千兆口之间的IP层网络通信。
[Abstract]:XDNP network processor is a monolithic multiprocessor system, which contains a large number of hardware modules used to process network protocols, multi-core multi-thread scheduling module, and bus arbitration module. Therefore, in the process of network processor function verification, the simulation method based on EDA tool is inefficient and the verification time is long. FPGA prototype verification verifies the correctness of chip design by building a real application environment, which overcomes the shortcomings of system level verification based on simulator, such as slow simulation speed and incomplete verification, which makes the verification work faster and more comprehensive. Based on the above purpose, this paper focuses on the design of FPGA prototype verification platform for XDNP network processor. In this paper, hardware verification schemes are divided into two types: FPGA prototype verification and MPE-BUS chip verification. In the FPGA prototype verification scheme, all the functions of XDNP are realized by FPGA chip. In the verification scheme of MPE-BUS chip, the core part of XDNP system, that is, six isomorphism packet processing engine PE and on-chip bus, is processed by eASIC Nextreme90nm technology, and the MPE-BUS chip is obtained. The remaining functions are realized by FPGA. In this paper, the design scheme of the verification platform is put forward, the schematic design of the XDNP-DEMODOARD board is completed, and the hardware design of the verification platform is realized. Based on the L3fwd8_1f and L3fwd2f reference programs attached to the Intel IXP1200 system, the XDNP system is verified by the platform, and the L3fwd8_1f reference program is used to test the 100-megabit routing function. L3fwd2f reference program is used to test gigabit to gigabit routing function. The results show that both FPGA prototype and MPE-BUS chip verification scheme can correctly realize IP layer network communication between 100m port and 100m port and between Gigabit port and gigabit port.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TN791
本文编号：2340942
[Abstract]:XDNP network processor is a monolithic multiprocessor system, which contains a large number of hardware modules used to process network protocols, multi-core multi-thread scheduling module, and bus arbitration module. Therefore, in the process of network processor function verification, the simulation method based on EDA tool is inefficient and the verification time is long. FPGA prototype verification verifies the correctness of chip design by building a real application environment, which overcomes the shortcomings of system level verification based on simulator, such as slow simulation speed and incomplete verification, which makes the verification work faster and more comprehensive. Based on the above purpose, this paper focuses on the design of FPGA prototype verification platform for XDNP network processor. In this paper, hardware verification schemes are divided into two types: FPGA prototype verification and MPE-BUS chip verification. In the FPGA prototype verification scheme, all the functions of XDNP are realized by FPGA chip. In the verification scheme of MPE-BUS chip, the core part of XDNP system, that is, six isomorphism packet processing engine PE and on-chip bus, is processed by eASIC Nextreme90nm technology, and the MPE-BUS chip is obtained. The remaining functions are realized by FPGA. In this paper, the design scheme of the verification platform is put forward, the schematic design of the XDNP-DEMODOARD board is completed, and the hardware design of the verification platform is realized. Based on the L3fwd8_1f and L3fwd2f reference programs attached to the Intel IXP1200 system, the XDNP system is verified by the platform, and the L3fwd8_1f reference program is used to test the 100-megabit routing function. L3fwd2f reference program is used to test gigabit to gigabit routing function. The results show that both FPGA prototype and MPE-BUS chip verification scheme can correctly realize IP layer network communication between 100m port and 100m port and between Gigabit port and gigabit port.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TN791
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