椭圆曲线密码处理器的高效并行处理架构研究与设计
发布时间：2018-11-19 11:03
【摘要】：为了解决当前椭圆曲线密码处理器普遍存在灵活性低、资源占用大的问题,该文采用统计建模的方式,以面积-时间(AT)综合性能指标为指导,提出了一种面向椭圆曲线密码并行处理架构的量化评估方式,并确定3路异构并行处理架构可使处理器综合性能达到最优。其次,该文提出一个分离分级式存储结构和一个运算资源高度复用的模运算单元,可增强存储器的访问效率和运算资源的利用率。在90 nm CMOS工艺下综合,该文处理器的面积为1.62 mm~2,完成一次GF(2~(571))和GF(p~(521))上的点乘运算分别需要2.26 ms/612.4μJ和2.63 ms/665.4μJ。与同类设计相比,该文处理器不仅具有较高的灵活性、可伸缩性,而且其芯片面积和运算速度达到了很好的折中。
[Abstract]:In ord to solve that problem that the current elliptic curve password processor is low in flexibility and large in resource occupation, a statistical modeling method is adopted to guide the comprehensive performance index of the area-time (AT), In this paper, a quantitative evaluation method for elliptic curve code parallel processing architecture is proposed, and the three-way heterogeneous parallel processing architecture is determined to make the comprehensive performance of the processor optimal. Secondly, this paper proposes a separate hierarchical storage structure and a high-level multiplexing model arithmetic unit, which can enhance the access efficiency of the memory and the utilization rate of the operation resources. In the process of 90 nm CMOS, the area of the processor is 1.62 mm ~ 2, and the point multiplication on GF (2 ~ (571)) and GF (p ~ (521)) needs to be 2.26 ms/ 612.4uJ and 2.63ms/ 664.mu. J respectively. Compared with the same kind of design, the processor not only has high flexibility and scalability, and the chip area and the operation speed of the chip are very good compromise.
【作者单位】： 解放军信息工程大学;复旦大学专用集成电路与系统国家重点实验室;
【基金】：国家自然科学基金(61404175)~~
【分类号】：TP332
，
本文编号：2342109
[Abstract]:In ord to solve that problem that the current elliptic curve password processor is low in flexibility and large in resource occupation, a statistical modeling method is adopted to guide the comprehensive performance index of the area-time (AT), In this paper, a quantitative evaluation method for elliptic curve code parallel processing architecture is proposed, and the three-way heterogeneous parallel processing architecture is determined to make the comprehensive performance of the processor optimal. Secondly, this paper proposes a separate hierarchical storage structure and a high-level multiplexing model arithmetic unit, which can enhance the access efficiency of the memory and the utilization rate of the operation resources. In the process of 90 nm CMOS, the area of the processor is 1.62 mm ~ 2, and the point multiplication on GF (2 ~ (571)) and GF (p ~ (521)) needs to be 2.26 ms/ 612.4uJ and 2.63ms/ 664.mu. J respectively. Compared with the same kind of design, the processor not only has high flexibility and scalability, and the chip area and the operation speed of the chip are very good compromise.
【作者单位】： 解放军信息工程大学;复旦大学专用集成电路与系统国家重点实验室;
【基金】：国家自然科学基金(61404175)~~
【分类号】：TP332
，
本文编号：2342109
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