一种改进的高性能处理器网络子系统架构设计
发布时间：2018-11-20 12:23
【摘要】：针对传统处理器网络子系统在高速网络环境下的性能瓶颈,特别是BD管理效率低、数据传输延迟大等问题,提出一种改进的网络子系统架构。该架构将BD管理功能从NIC上移至处理器,并扩展了BD信息,同时增加了cache的查找和读后无效操作。通过Simics模拟器对系统架构进行了仿真及评估。实验结果表明,较传统的架构和采用DCA技术的架构相比,改进后架构在取得了更高带宽利用率的同时,降低了CPU利用率,更好地保持了性能和资源的平衡。
[Abstract]:Aiming at the performance bottleneck of traditional processor network subsystem in high speed network environment, especially the problems of low efficiency of BD management and large delay of data transmission, an improved network subsystem architecture is proposed. The architecture moves the BD management function from NIC to processor, extends BD information, and adds cache lookup and post-reading invalid operations. The system architecture is simulated and evaluated by Simics simulator. The experimental results show that compared with the traditional architecture and the architecture using DCA technology, the improved architecture not only achieves higher bandwidth utilization, but also reduces the CPU utilization, and maintains a better balance between performance and resources.
【作者单位】： 西安微电子技术研究所;
【分类号】：TP332
本文编号：2344905
[Abstract]:Aiming at the performance bottleneck of traditional processor network subsystem in high speed network environment, especially the problems of low efficiency of BD management and large delay of data transmission, an improved network subsystem architecture is proposed. The architecture moves the BD management function from NIC to processor, extends BD information, and adds cache lookup and post-reading invalid operations. The system architecture is simulated and evaluated by Simics simulator. The experimental results show that compared with the traditional architecture and the architecture using DCA technology, the improved architecture not only achieves higher bandwidth utilization, but also reduces the CPU utilization, and maintains a better balance between performance and resources.
【作者单位】： 西安微电子技术研究所;
【分类号】：TP332
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