面向DSP软加固循环代码的低功耗优化技术
发布时间：2018-11-22 10:03
【摘要】：近年来,随着科学技术的发展,以及人们对计算机更高的性能要求,采用商用器件来构建航天设备已经成为了国内外的发展趋势。相比于传统的航空航天级的芯片器件,商用器件具有性能超群、成本低廉、数量充裕等优势,能够满足航空航天设备日益增长的性能需求。但恶劣的太空环境会给星载计算机的可靠性带来十分严峻的问题,商用器件的缺陷在于抗辐照能力低,在恶劣的太空环境下,商用器件受高能粒子辐照极易发生故障。而软件容错技术让我们在不利用抗辐照专用芯片的条件下也可以取得可靠性保证。但是,软件容错技术的大量复算工作会大大提高系统的能量开销,如何削减能耗成为一个必须解决的问题。本文在研究了控制流和数据流软件容错算法的基础上,针对高性能的商用DSP-TMS320C6748硬件实验平台,提出了软加固高性能处理器的功耗优化方法。本文的主要工作和创新有以下几点:(1)深入研究了软件容错技术的数据流和控制流容错算法以及功耗优化技术,总结了DSP硬件平台的特点,设计了从软加固前至软加固算法再至软加固后的三阶段、全方位的针对软件容错进行性能和功耗优化的优化流程。(2)分析应用了基于C/C++语言和基于汇编语言的低功耗优化方法。面向C/C++语言,针对循环代码,总结了包括循环展开、循环合并、循环分块等低功耗优化方法。在汇编语言下,针对C6000系列DSP独特的线性汇编,总结了内联、嵌入等低功耗优化方法。通过实验验证,在进行软件容错处理之前,使用以上方法进行优化,平均性能提升幅度为36.2%。(3)分析软加固算法的特点及流程,结合DSP的流水特点,面向DSP硬件平台,对软加固算法进行改进,提出了基于DSP线性汇编的循环优化算法SFLOA,以增加容错延迟为代价,在不降低错误检测率的同时,能更充分利用DSP的流水线,大幅降低程序运行周期数,降低系统总能量消耗。通过实验验证,在容错过程中,使用SFLOA算法对容错算法的改进,可以使平均功耗优化幅度达到79.995%,平均性能提升幅度为57.76%。(4)在软加固处理之后的优化阶段中,提出了基于软加固循环的动态电压调度算法LFDVS。该算法以容错后的循环为基本单位,对每个循环分配不同的处理器频率,结合对复杂循环的静态调度和对简单循环的动态调度,在保证检错率的前提下,能最大化利用CPU的空闲时间来进行降低电压和频率。通过实验数据可以看出该算法能显著地降低能量开销。
[Abstract]:In recent years, with the development of science and technology, as well as the higher performance requirements of computers, the use of commercial devices to build aerospace equipment has become a trend of development at home and abroad. Compared with the conventional chip devices, commercial devices have the advantages of superior performance, low cost and abundant quantity, which can meet the increasing performance requirements of aerospace equipment. However, the bad space environment will bring serious problems to the reliability of spaceborne computer. The defect of commercial devices lies in their low radiation resistance. In the harsh space environment, commercial devices are prone to failure when irradiated by high-energy particles. Software fault-tolerant technology allows us to obtain reliability guarantees without the use of radiation-resistant dedicated chips. However, a large amount of software fault-tolerant technology will greatly increase the energy cost of the system, how to reduce energy consumption has become a problem that must be solved. Based on the research of fault-tolerant algorithms for control flow and data flow software, this paper presents a power optimization method for high performance DSP-TMS320C6748 processors based on high performance commercial DSP-TMS320C6748 hardware experimental platform. The main work and innovations of this paper are as follows: (1) the fault-tolerant algorithms of data flow and control flow and the power optimization technology of software fault-tolerant technology are deeply studied, and the characteristics of DSP hardware platform are summarized. The three stages from the soft reinforcement to the soft reinforcement algorithm and to the soft reinforcement algorithm are designed. The software fault-tolerant performance and power optimization process is all-around. (2) A low power optimization method based on C / C language and assembly language is applied. For C / C language, low power optimization methods including loop expansion, loop merging and loop block are summarized for cyclic code. Based on the unique linear assembly of C6000 series DSP, low power optimization methods such as inline and embedding are summarized in assembly language. The experimental results show that before the software fault-tolerant processing, the above methods are used to optimize, and the average performance improvement range is 36.2. (3) the characteristics and flow of the soft reinforcement algorithm are analyzed, combined with the flow characteristics of DSP. For the hardware platform of DSP, the soft reinforcement algorithm is improved, and the cyclic optimization algorithm SFLOA, based on DSP linear assembly is proposed, which can make full use of the pipeline of DSP without reducing the error detection rate at the cost of increasing fault tolerant delay. Greatly reduce the number of program running cycles, reduce the total energy consumption of the system. Experimental results show that in the process of fault tolerance, the improved SFLOA algorithm can improve the average power consumption to 79.9955. The average performance improvement range is 57.76. (4) in the optimization stage after soft reinforcement treatment, a dynamic voltage scheduling algorithm LFDVS. based on soft reinforcement cycle is proposed. The algorithm takes fault-tolerant cycles as the basic unit, assigns different processor frequencies to each cycle, combines the static scheduling of complex cycles and the dynamic scheduling of simple loops, and ensures the error detection rate. Can maximize the use of CPU idle time to reduce the voltage and frequency. The experimental data show that the algorithm can significantly reduce the energy cost.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：V446;TP302.7
，
本文编号：2348964
[Abstract]:In recent years, with the development of science and technology, as well as the higher performance requirements of computers, the use of commercial devices to build aerospace equipment has become a trend of development at home and abroad. Compared with the conventional chip devices, commercial devices have the advantages of superior performance, low cost and abundant quantity, which can meet the increasing performance requirements of aerospace equipment. However, the bad space environment will bring serious problems to the reliability of spaceborne computer. The defect of commercial devices lies in their low radiation resistance. In the harsh space environment, commercial devices are prone to failure when irradiated by high-energy particles. Software fault-tolerant technology allows us to obtain reliability guarantees without the use of radiation-resistant dedicated chips. However, a large amount of software fault-tolerant technology will greatly increase the energy cost of the system, how to reduce energy consumption has become a problem that must be solved. Based on the research of fault-tolerant algorithms for control flow and data flow software, this paper presents a power optimization method for high performance DSP-TMS320C6748 processors based on high performance commercial DSP-TMS320C6748 hardware experimental platform. The main work and innovations of this paper are as follows: (1) the fault-tolerant algorithms of data flow and control flow and the power optimization technology of software fault-tolerant technology are deeply studied, and the characteristics of DSP hardware platform are summarized. The three stages from the soft reinforcement to the soft reinforcement algorithm and to the soft reinforcement algorithm are designed. The software fault-tolerant performance and power optimization process is all-around. (2) A low power optimization method based on C / C language and assembly language is applied. For C / C language, low power optimization methods including loop expansion, loop merging and loop block are summarized for cyclic code. Based on the unique linear assembly of C6000 series DSP, low power optimization methods such as inline and embedding are summarized in assembly language. The experimental results show that before the software fault-tolerant processing, the above methods are used to optimize, and the average performance improvement range is 36.2. (3) the characteristics and flow of the soft reinforcement algorithm are analyzed, combined with the flow characteristics of DSP. For the hardware platform of DSP, the soft reinforcement algorithm is improved, and the cyclic optimization algorithm SFLOA, based on DSP linear assembly is proposed, which can make full use of the pipeline of DSP without reducing the error detection rate at the cost of increasing fault tolerant delay. Greatly reduce the number of program running cycles, reduce the total energy consumption of the system. Experimental results show that in the process of fault tolerance, the improved SFLOA algorithm can improve the average power consumption to 79.9955. The average performance improvement range is 57.76. (4) in the optimization stage after soft reinforcement treatment, a dynamic voltage scheduling algorithm LFDVS. based on soft reinforcement cycle is proposed. The algorithm takes fault-tolerant cycles as the basic unit, assigns different processor frequencies to each cycle, combines the static scheduling of complex cycles and the dynamic scheduling of simple loops, and ensures the error detection rate. Can maximize the use of CPU idle time to reduce the voltage and frequency. The experimental data show that the algorithm can significantly reduce the energy cost.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：V446;TP302.7
，
本文编号：2348964
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