抗多节点翻转的存储器设计
发布时间：2018-11-23 15:57
【摘要】：随着集成电路的迅猛发展，制造工艺尺寸进入了纳米级，使得集成电路系统越来越容易受到来自地面环境和太空环境中辐射效应特别是单粒子翻转（SEU）的影响。而静态随机存储器（SRAM）因其速度快、功耗低等优良性能也随着工业的发展而占据越来越重要的位置，，然而它也是集成电路系统中对SEU最为敏感的部分，因此业界也一直在寻找行之有效的SRAM抗辐射加固技术。 本文首先研究分析了SRAM工艺级加固、版图级加固、系统级加固和电路级加固方案以及各个抗SEU加固存储单元工作机理。基于目前纳米工艺尺寸下这些加固存储单元鲜有抗多节点翻转能力，本文最终采用改进的DICE单元即TDICE单元设计了具有抗多节点翻转能力的容量为128x8bit的SRAM。本文详细研究了TDICE单元的性能及SMIC65nm标准单元库的建库流程，将TDICE按照标单元库的设计要求设计为标准库单元，并通过了验证使其能够被EDA工具识别。其次详细介绍了SRAM外围电路的设计，并进行了各电路的功能仿真验证，然后将各部分电路与存储阵列搭建SRAM整体电路。外围电路主要包括行列译码电路、灵敏放大电路、写控制电路及数据输入输出电路等。仿真结果证明SRAM功能正确。 最后基于SMIC65nm工艺，设计实现了各个电路模块及SRAM整体电路的版图和后仿真验证，结果表明1.2V工作电压下，SRAM能够在100MHz频率下进行正确的读写操作，并具有抗多节点翻转能力。
[Abstract]:With the rapid development of integrated circuits, the fabrication process size has entered the nanometer level, which makes the integrated circuit system more and more vulnerable to the radiation effects from the ground environment and the space environment, especially the single-particle flip (SEU). The static random access memory (SRAM) occupies an increasingly important position with the development of industry because of its high speed and low power consumption. However, it is also the most sensitive part of integrated circuit system to SEU. Therefore, the industry has been looking for effective SRAM radiation reinforcement technology. Firstly, this paper studies and analyzes the reinforcement schemes of SRAM technology grade, layout level, system level and circuit level, and the working mechanism of each anti-SEU reinforcement storage cell. Based on the fact that these strengthened storage cells have few anti-multi-node flip ability under the current nanometer process size, the improved DICE unit, TDICE cell, is used to design the SRAM. with the capacity of 128x8bit with the anti-multi-node flip ability. In this paper, the performance of TDICE unit and the process of building SMIC65nm standard cell library are studied in detail. TDICE is designed as standard library unit according to the design requirements of the standard unit library, and it can be recognized by EDA tools through verification. Secondly, the design of the peripheral circuit of SRAM is introduced in detail, and the function of each circuit is verified by simulation. Then, the whole circuit of SRAM is built with each part of the circuit and the memory array. Peripheral circuits include column decoding circuit, sensitive amplifier circuit, write control circuit and data input and output circuit. The simulation results show that the SRAM function is correct. Finally, based on SMIC65nm process, the layout and post-simulation of each circuit module and SRAM circuit are designed and implemented. The results show that SRAM can read and write correctly at 100MHz frequency under 1.2 V operating voltage. And it has the ability to resist multi-node flipping.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333
本文编号：2351976
[Abstract]:With the rapid development of integrated circuits, the fabrication process size has entered the nanometer level, which makes the integrated circuit system more and more vulnerable to the radiation effects from the ground environment and the space environment, especially the single-particle flip (SEU). The static random access memory (SRAM) occupies an increasingly important position with the development of industry because of its high speed and low power consumption. However, it is also the most sensitive part of integrated circuit system to SEU. Therefore, the industry has been looking for effective SRAM radiation reinforcement technology. Firstly, this paper studies and analyzes the reinforcement schemes of SRAM technology grade, layout level, system level and circuit level, and the working mechanism of each anti-SEU reinforcement storage cell. Based on the fact that these strengthened storage cells have few anti-multi-node flip ability under the current nanometer process size, the improved DICE unit, TDICE cell, is used to design the SRAM. with the capacity of 128x8bit with the anti-multi-node flip ability. In this paper, the performance of TDICE unit and the process of building SMIC65nm standard cell library are studied in detail. TDICE is designed as standard library unit according to the design requirements of the standard unit library, and it can be recognized by EDA tools through verification. Secondly, the design of the peripheral circuit of SRAM is introduced in detail, and the function of each circuit is verified by simulation. Then, the whole circuit of SRAM is built with each part of the circuit and the memory array. Peripheral circuits include column decoding circuit, sensitive amplifier circuit, write control circuit and data input and output circuit. The simulation results show that the SRAM function is correct. Finally, based on SMIC65nm process, the layout and post-simulation of each circuit module and SRAM circuit are designed and implemented. The results show that SRAM can read and write correctly at 100MHz frequency under 1.2 V operating voltage. And it has the ability to resist multi-node flipping.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333
【参考文献】
相关期刊论文 前3条
1 施亮;高宁;于宗光;;深亚微米SRAM存储单元静态噪声容限研究[J];电子与封装;2007年05期
2 徐睿;顾展弘;罗静;;一种抗辐射加固检错纠错电路的设计[J];微电子学;2010年04期
3 QIN JunRui;LI DaWei;CHEN ShuMing;;A novel layout for single event upset mitigation in advanced CMOS SRAM cells[J];Science China(Technological Sciences);2013年01期
本文编号：2351976
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2351976.html
