浮点融合乘加部件设计分析与尾数加电路定制设计

发布时间：2018-11-28 18:08

【摘要】：浮点融合乘加部件(MAF)是现代微处理器中的核心部件,它的运算速度直接影响到微处理器的性能。浮点融合乘加部件的计算延时大、结构规模复杂并且功耗相对较高,处在关键路径上。对浮点融合乘加部件的研究具有较高的应用价值。本文通过对X处理器中的64位浮点融合乘加部件进行研究和优化设计,在支持浮点运算与整数运算的基础上,对其中的关键模块进行了分析与研究,综合分析确认原设计的108位尾数加较大的制约了整个浮点融合乘加部件的性能,本文通过改进尾数加的结构并对其进行定制设计,使得浮点融合乘加部件整体性能得到提升。本课题的主要工作和贡献如下： 1.DC综合分析,查找分析关键路径,寻找提升整体浮点融合乘加部件性能的方法； 2.在尾数加设计中最后两级运算分别采用了进位选择加法器结构和循环进位(End-Around-Carry)结构,其中进位选择结构中把进位为“0”和进位为“1”中相同的部分共用使得面积进一步减小,并且性能不受影响；采用最后一级循环进位结构使得在加法运算时省去了一步加数求补和最终结果的求反加1过程； 3.在40nm工艺下对定制完成的108位尾数加进行了时序验证并得出最终结果。设计所占面积为1872.82um2,最坏条件下,尾数加部分运算延迟为350ps,并且相对于改进前时的面积减小了20%并且性能提升23%。从而使得尾数加部分不是制约浮点融合乘加部件性能的关键路径。
[Abstract]:The floating-point fusion multiplication and addition component (MAF) is the core component in modern microprocessors, and its operation speed directly affects the performance of microprocessors. The floating-point fusion multiplicative component has the advantages of large computational delay, complex structure and relatively high power consumption, so it is in the critical path. The research of floating-point fusion multiplying and adding parts has high application value. This paper studies and optimizes the 64-bit floating-point fusion multiplication and addition part in X processor, and analyzes and studies the key modules on the basis of supporting floating-point operation and integer operation. It is confirmed by comprehensive analysis that the performance of the whole floating-point fusion multiplicator is restricted by the 108-bit Mantissa added in the original design. By improving the structure of the Mantissa addition and customizing it, the overall performance of the floating-point fusion multiplicative adders is improved. The main work and contributions of this thesis are as follows: 1.DC comprehensive analysis, finding and analyzing key paths, searching for methods to improve the performance of integral floating-point fusion multiplication plus components; 2. In the last two stages of the Mantissa addition design, the carry-selective adder structure and the cyclic carry (End-Around-Carry) structure are used, respectively. In the carry-selection structure, the same parts of carry "0" and carry "1" make the area decrease further, and the performance is not affected. The last stage cyclic carry structure is adopted so that the one-step addition complement and the inverse addition of the final result are eliminated in addition operation; 3. The addition of 108-bit Mantissa was verified in 40nm process and the final result was obtained. The area occupied by the design is 1872. 82um 2. In the worst case, the Mantissa plus part operation delay is 350 pss, and the area is reduced by 20% compared with that before the improvement, and the performance is improved by 23%. Therefore, the addition of Mantissa is not the key path to restrict the performance of floating-point fusion multiplication.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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