XDNP网络处理器快速总线接口FBI设计与实现
发布时间：2018-12-05 19:57
【摘要】：随着互联网技术的快速发展，网络处理器作为现代网络系统的核心设备，正在向着多核片上系统的方向发展；随着微电子技术的迅猛发展，如今已进入了超深亚微米、纳米时代，，为了满足性能、功耗和成本的需求，芯片的物理实现也越来越复杂。 作为网络处理器的数据交换枢纽，快速总线接口FBI承载了网络端口和包处理引擎以及SDRAM单元之间众多的数据通路和控制通路，它是实现网络处理器与外部数据交换的平台，因此快速总线接口FBI是决定网络处理器性能的关键单元之一。如何设计并实现快速总线接口FBI对于高性能网络处理器系统显得至关重要。 本文首先重点描述了在快端口模式中XDNP网络处理器的工作机制，规范了快速总线接口FBI的功能和体系框架：生成微包的序列号，协助包处理引擎PE保持数据分组的顺序；使用了双口结构的SRAM作为数据缓存单元，解决了异步时钟域之间的数据同步化问题；采用了DMA的方式，减轻了包处理引擎PE的工作负担；设计了PUSH/PULL引擎的命令队列，对来自于包处理引擎PE与SDRAM控制器的指令代码进行仲裁与排队操作，这样解决了包处理引擎PE可能同时有多个线程向快速总线接口FBI发出转发数据包指令的问题。 接着本文完成了快速总线接口FBI的详细设计方案，分别介绍了PUSH/PULL引擎、接收/发送控制器、接收/发送缓存的设计，并从综合约束、设计优化等方面给出了快速总线接口FBI的具体实现和优化，详细分析了时序违例和优化的方法。在最坏条件下快速总线接口FBI的最高工作频率达到233MHz，优于系统设计目标频率要求。最后根据综合得到的网表和约束文件在SMICCMOS130nm工艺下完成了快速总线接口FBI的物理实现工作。
[Abstract]:With the rapid development of Internet technology, network processor, as the core equipment of modern network system, is developing towards the direction of multi-core on-chip system. With the rapid development of microelectronics technology, the physical realization of chips is becoming more and more complicated in order to meet the demand of performance, power consumption and cost. As the data exchange hub of the network processor, the fast bus interface (FBI) carries many data paths and control paths between the network port, packet processing engine and SDRAM unit. It is the platform to realize the data exchange between the network processor and the external data. So the fast bus interface (FBI) is one of the key units to determine the performance of the network processor. How to design and implement fast bus interface (FBI) is very important for high performance network processor system. In this paper, the working mechanism of XDNP network processor in fast port mode is described, and the function and architecture of fast bus interface (FBI) are standardized. The sequence number of micropacket is generated to help the packet processing engine (PE) keep the order of data packet. The dual-port structure of SRAM is used as the data buffer unit to solve the problem of data synchronization between asynchronous clock domains, and the way of DMA is adopted to reduce the workload of packet processing engine PE. The command queue of PUSH/PULL engine is designed to arbitrate and queue the instruction code from packet processing engine PE and SDRAM controller. This solves the problem that the packet processing engine PE may have multiple threads simultaneously sending forward packet instructions to the fast bus interface FBI. Then, this paper completes the detailed design of FBI, introduces the design of PUSH/PULL engine, receiver / transmitter controller, receive / transmit cache, and synthesizes constraints. The realization and optimization of fast bus interface FBI are given, and the methods of timing violation and optimization are analyzed in detail. In the worst case, the maximum operating frequency of the fast bus interface FBI is 233MHz, which is better than the target frequency requirement of the system design. Finally, the physical implementation of the fast bus interface (FBI) under the SMICCMOS130nm process is completed according to the network table and constraint file.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7;TN432
本文编号：2365391
[Abstract]:With the rapid development of Internet technology, network processor, as the core equipment of modern network system, is developing towards the direction of multi-core on-chip system. With the rapid development of microelectronics technology, the physical realization of chips is becoming more and more complicated in order to meet the demand of performance, power consumption and cost. As the data exchange hub of the network processor, the fast bus interface (FBI) carries many data paths and control paths between the network port, packet processing engine and SDRAM unit. It is the platform to realize the data exchange between the network processor and the external data. So the fast bus interface (FBI) is one of the key units to determine the performance of the network processor. How to design and implement fast bus interface (FBI) is very important for high performance network processor system. In this paper, the working mechanism of XDNP network processor in fast port mode is described, and the function and architecture of fast bus interface (FBI) are standardized. The sequence number of micropacket is generated to help the packet processing engine (PE) keep the order of data packet. The dual-port structure of SRAM is used as the data buffer unit to solve the problem of data synchronization between asynchronous clock domains, and the way of DMA is adopted to reduce the workload of packet processing engine PE. The command queue of PUSH/PULL engine is designed to arbitrate and queue the instruction code from packet processing engine PE and SDRAM controller. This solves the problem that the packet processing engine PE may have multiple threads simultaneously sending forward packet instructions to the fast bus interface FBI. Then, this paper completes the detailed design of FBI, introduces the design of PUSH/PULL engine, receiver / transmitter controller, receive / transmit cache, and synthesizes constraints. The realization and optimization of fast bus interface FBI are given, and the methods of timing violation and optimization are analyzed in detail. In the worst case, the maximum operating frequency of the fast bus interface FBI is 233MHz, which is better than the target frequency requirement of the system design. Finally, the physical implementation of the fast bus interface (FBI) under the SMICCMOS130nm process is completed according to the network table and constraint file.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7;TN432
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