基于FPGA浮点运算器的研究

发布时间：2018-12-09 10:35

【摘要】：浮点运算在各种工程计算和科学计算中的应用非常广泛。在一些对速度要求较高的情况下,必须采用一个专门的浮点运算器。 到目前为止,由于现场可编程门阵列(FPGA)发展迅速,应用EDA技术,设计浮点运算,已成为研究热点,所以本文是基于FPGA来研究浮点运算的。主要研究了IEEE754标准的浮点数的表示及加减、乘、除运算规则,结合已有的浮点运算硬件模型,分析了用Verilog HDL语言程序实现的64位浮点数的加减、乘、除基本的运算功能的实现方法,并在QuartusⅡ环境下,将程序进行编译、综合、调试,做出功能和时序仿真；同时用C语言编写程序,用来实现将两个双精度浮点数进行加减、乘、除,并将结果转换成符合IEEE754标准的双精度浮点数的二进制形式输出,其目的是用这个结果来验证仿真结果,如果结果一致,说明Verilog HDL语言程序正确。由于条件有限,无法将64位浮点运算的程序直接下载到现有FPGA上,所以最后以浮点加减法为例,将浮点位数缩短成7位,修改程序,再进行仿真、下载与配置。
[Abstract]:Floating-point operations are widely used in various engineering and scientific calculations. A special floating-point operator must be used in some cases with high speed requirements. So far, due to the rapid development of field programmable gate array (FPGA), the application of EDA technology to design floating-point operations has become a research hotspot. Therefore, this paper is based on FPGA to study floating-point operations. This paper mainly studies the representation, addition and subtraction, multiplication and division rules of IEEE754 standard floating-point number, combining with the existing floating-point operation hardware model, analyzes the addition and subtraction and multiplication of 64-bit floating-point number realized by Verilog HDL program. In addition to the basic operation function realization method, and under the Quartus 鈪，

本文编号：2369240