面向三维多核微处理器的NoC拓扑结构研究
发布时间：2018-12-17 04:40
【摘要】：多核时代微处理器设计面临的功耗、访存、互连等问题进一步恶化。三维集成电路（3D IC）是一种新的集成电路工艺，通过将多层硅片使用硅通孔（TSV）连接可以增加单芯片封装内的硅片资源、缩短硅片间全局连线，使得芯片内部能够容纳更多核心与相关资源。片上网络（NoC）则是一种面向多核与众核处理器通讯需求的结构化互连设计方法。3D IC和NoC都是大规模集成电路设计发展重要方向。将两者结合的三维片上网络（3D NoC）可以同时发挥3D IC和NoC的互连部件多、带宽高、延迟低的优势，是当前研究的热点之一。 现有三维片上网络拓扑结构的研究，都是针对4层左右硅片堆叠无法进一步扩展。然而10层以上硅片堆叠的可能性已经得到证明。本文利用三维集成电路中硅通孔（TSV）具有延迟短、功耗小的特性，针对10层以上硅片堆叠的三维片上网络，设计了一种新的拓扑结构3DE-Mesh。通过实验数据的分析，证明3DE-Mesh在性能和可扩展性方面都适合于10层以上硅片堆叠的三维集成电路。 现有3D NoC的研究，基本上都是采用固定结构的路由器，网络性能会随堆叠层数增加而下降，同时没有充分利用3D IC中硅通孔（TSV）延迟短、功耗小的特性。为了充分发掘TSV的特性，并面向未来多层TSV堆叠扩展需求，，本文提出了一种硅片间扩展路由器（EIDR），并设计了使用该路由器构建的硅片间单跳步（SHID）体系结构。SHID能通过增加TSV数量获得性能改善。实验数据的分析表明，与3D-Mesh和NoC-Bus这两种已有的3D NoC结构相比SHID结构有以下特点：1）SHID体系结构的延迟较低，4层堆叠时比3D-Mesh低15.1%，比NoC-Bus低11.5%；2）SHID体系结构的功耗与NoC-Bus相当，比3D-Mesh低10%左右；3）SHID体系结构的吞吐率随堆叠层数增加下降缓慢，16层堆叠时吞吐率比3D-Mesh高66.98%，比Noc-Bus高314.49%。 多层堆叠的三维拓扑结构3DE-Mesh与SHID体系结构弥补了现有三维NOC结构研究中扩展能力不足的缺点，同时具备性能和可扩展性的优势，是未来3DNoC体系结构良好设计选择。
[Abstract]:The power consumption, memory access, interconnection and other problems of microprocessor design in multi-core era are getting worse. Three-dimensional integrated circuit (3D IC) is a new integrated circuit technology. By connecting multilayer silicon wafer with silicon through hole (TSV), we can increase the silicon chip resource in single chip package and shorten the global connection between silicon wafers. So that the chip can accommodate more core and related resources. On-chip network (NoC) is a kind of structured interconnect design method to meet the communication requirements of multi-core and multi-core processors. 3D IC and NoC are both important directions in the development of VLSI design. The combination of 3D NoC and 3D IC can bring into play the advantages of many interconnecting parts, high bandwidth and low delay of 3D IC and NoC, so it is one of the hot research topics at present. The existing research of three-dimensional on-chip network topology is aimed at the 4-layer stack of silicon wafers which can not be further expanded. However, the possibility of stacking more than 10 layers of silicon wafers has been proved. In this paper, a new topology 3DE-Mesh. is designed for the three dimensional on-chip network with more than 10 layers of silicon wafers, which has the characteristics of short delay and low power consumption of silicon through hole (TSV) in 3D integrated circuits. Through the analysis of experimental data, it is proved that 3DE-Mesh is suitable for three dimensional integrated circuits with more than 10 layers of silicon chips in terms of performance and extensibility. The existing researches on 3D NoC are based on fixed structure routers, and the network performance will decrease with the increase of stacking layers. At the same time, it does not make full use of the characteristics of short (TSV) delay and low power consumption in 3D IC. In order to fully explore the characteristics of TSV and to meet the needs of multilayer TSV stack expansion in the future, this paper proposes a kind of (EIDR), for interwafer expansion router. A single step (SHID) architecture with this router is designed. SHID can be improved by increasing the number of TSV acquired. The analysis of experimental data shows that compared with 3D-Mesh and NoC-Bus, the SHID structure has the following characteristics: 1) the delay of SHID architecture is lower, 15.1 layers lower than 3D-Mesh and 11.5% lower than NoC-Bus; 2) the power consumption of SHID architecture is about the same as that of NoC-Bus, which is about 10% lower than that of 3D-Mesh; 3) the throughput of the SHID architecture decreases slowly with the increase of the number of stacked layers. The throughput of 16 layers is 66.98 higher than that of 3D-Mesh and 314.49 higher than that of Noc-Bus. Multi-layer stacked 3D topology 3DE-Mesh and SHID architecture make up for the shortcomings of the existing 3D NOC architecture in the research of the lack of extensibility. At the same time, it has the advantages of performance and scalability. It is a good design choice for the future 3DNoC architecture.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
本文编号：2383671
[Abstract]:The power consumption, memory access, interconnection and other problems of microprocessor design in multi-core era are getting worse. Three-dimensional integrated circuit (3D IC) is a new integrated circuit technology. By connecting multilayer silicon wafer with silicon through hole (TSV), we can increase the silicon chip resource in single chip package and shorten the global connection between silicon wafers. So that the chip can accommodate more core and related resources. On-chip network (NoC) is a kind of structured interconnect design method to meet the communication requirements of multi-core and multi-core processors. 3D IC and NoC are both important directions in the development of VLSI design. The combination of 3D NoC and 3D IC can bring into play the advantages of many interconnecting parts, high bandwidth and low delay of 3D IC and NoC, so it is one of the hot research topics at present. The existing research of three-dimensional on-chip network topology is aimed at the 4-layer stack of silicon wafers which can not be further expanded. However, the possibility of stacking more than 10 layers of silicon wafers has been proved. In this paper, a new topology 3DE-Mesh. is designed for the three dimensional on-chip network with more than 10 layers of silicon wafers, which has the characteristics of short delay and low power consumption of silicon through hole (TSV) in 3D integrated circuits. Through the analysis of experimental data, it is proved that 3DE-Mesh is suitable for three dimensional integrated circuits with more than 10 layers of silicon chips in terms of performance and extensibility. The existing researches on 3D NoC are based on fixed structure routers, and the network performance will decrease with the increase of stacking layers. At the same time, it does not make full use of the characteristics of short (TSV) delay and low power consumption in 3D IC. In order to fully explore the characteristics of TSV and to meet the needs of multilayer TSV stack expansion in the future, this paper proposes a kind of (EIDR), for interwafer expansion router. A single step (SHID) architecture with this router is designed. SHID can be improved by increasing the number of TSV acquired. The analysis of experimental data shows that compared with 3D-Mesh and NoC-Bus, the SHID structure has the following characteristics: 1) the delay of SHID architecture is lower, 15.1 layers lower than 3D-Mesh and 11.5% lower than NoC-Bus; 2) the power consumption of SHID architecture is about the same as that of NoC-Bus, which is about 10% lower than that of 3D-Mesh; 3) the throughput of the SHID architecture decreases slowly with the increase of the number of stacked layers. The throughput of 16 layers is 66.98 higher than that of 3D-Mesh and 314.49 higher than that of Noc-Bus. Multi-layer stacked 3D topology 3DE-Mesh and SHID architecture make up for the shortcomings of the existing 3D NOC architecture in the research of the lack of extensibility. At the same time, it has the advantages of performance and scalability. It is a good design choice for the future 3DNoC architecture.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332
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