基于OpenRISC1200 32位CPU的miniSoC系统设计和软硬件验证

发布时间：2018-12-20 06:01

【摘要】：在整个广泛的集成电路产业中，几乎每一个SoC内部都集成和应用了一款CPU。由于CPU设计技术的复杂性和高度保密性，商业化处理器及其IP核价格昂贵，同时，很少有公开的资料对内部逻辑实现进行详细介绍，若作为积累CPU设计经验、降低设计成本和技术门槛的研究对象不太适合。如果选择开源的CPU系列，会有较为完整的资料，这样的CPU目前也有不少，比如OpenRISC和LEON等，这里我们选择OpenRISC OR1200作为我们研究的对象。 OR1200是开放源代码处理器，为OpenCores组织基于GPL协议提供，其性能可以为一般的嵌入式系统使用。同时OpenCores组织和部分开源爱好者提供了比较完整的开放源代码IP核、开发资料供研究人员使用[40]。本论文先介绍计算机体系结构的基础内容，阐述计算机体系结构对嵌入式处理器设计和测试的重要性，主要为硬件和软件功能的划分，确定硬件和软件的分界。了解嵌入式处理器设计应考虑成本、价格和发展趋势，性能评估及基准测试程序。有助于软件程序设计人员编写出高质量程序，处理器设计人员能提供软件开发更好的设计架构确保其正常高效运行。本论文研究了OpenRISC的地址与寻址方式、指令集和指令格式，流水线等内容，详细研究了OR1200核心、Cache、MMU、DEBUG等组成的处理器最核心架构，各设计单元功能之间的数据交互和处理方式，，掌握典型处理器独立工作、软件调试等整体系统的设计能力。本论文对Wishbone总线协议及互连类型详细分析。Wishbone总线规范也是一种片上系统IP核互连体系结构，需要集成的IP核遵照总线规范协议，提供相同的公共逻辑接口，在大规模集成方面易于实施，易于重用，易于移植，同时验证和可靠性都得到了提高[1]。在分析完处理器架构后，设计miniSoC系统，并下载到FPGA硬件平台，基于Cygwin环境下进行软件开发环境和软件工具的移植和测试，实现了miniSoC系统的软硬件验证，此系统便于后续集成更多IP、并协同软件共同开发。
[Abstract]:Almost every SoC has integrated and applied a CPU. in the whole integrated circuit industry Because of the complexity and high confidentiality of CPU design technology, the commercial processor and its IP core are expensive. At the same time, there are few open data to introduce the implementation of internal logic in detail, if as a result of accumulating CPU design experience, The research object that reduces the design cost and the technical threshold is not suitable. If you choose the open source CPU series, there will be more complete information, such as the current CPU, such as OpenRISC and LEON, and so on, here we choose OpenRISC OR1200 as our research object. OR1200 is an open source processor for OpenCores organization based on GPL protocol, its performance can be used for general embedded systems. At the same time, the OpenCores organization and some open source enthusiasts provide a relatively complete open source IP core, development materials for researchers to use [40]. This paper first introduces the basic contents of computer architecture, expounds the importance of computer architecture for embedded processor design and testing, mainly for the division of hardware and software functions, and determines the distinction between hardware and software. Understand embedded processor design should consider cost, price and development trends, performance evaluation and benchmarking procedures. It is helpful for software programmers to write high quality programs, and processor designers can provide better design architecture for software development to ensure its normal and efficient operation. This paper studies the address and addressing mode of OpenRISC, instruction set and instruction format, pipeline and so on, and studies the core architecture of OR1200, Cache,MMU,DEBUG and so on in detail. The data exchange and processing between the functions of each design unit, master the design ability of the system such as the typical processor working independently, software debugging and so on. In this paper, the Wishbone bus protocol and the interconnection type are analyzed in detail. The Wishbone bus specification is also a kind of on-chip system IP core interconnection architecture. The IP core that needs to be integrated provides the same common logic interface according to the bus specification protocol. Large scale integration is easy to implement, easy to reuse, easy to transplant, at the same time, verification and reliability have been improved [1]. After analyzing the processor architecture, the miniSoC system is designed and downloaded to the FPGA hardware platform. The software development environment and software tools are transplanted and tested based on the Cygwin environment, and the software and hardware verification of the miniSoC system is realized. This system is convenient to integrate more IP, and develop together with software.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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