DSP芯片中的高能效FFT加速器
发布时间：2018-12-31 11:25
【摘要】：快速傅里叶变换(fast Fourier transform,FFT)是数字信号处理(digital signal processing,DSP)领域中最耗时的核心算法,该算法的计算性能和计算效率将影响整个应用的执行效率.因此,在DSP芯片上设计实现了一个基于矩阵转置操作的高能效可变长度FFT加速器,采用多种并行策略开发批量小规模FFT算法与大规模Cooley-Tukey FFT算法中指令级和任务级并行.设计"乒乓"多体数据存储器,重叠数据搬移和FFT计算之间的开销,提高FFT加速器计算效率.并基于此存储器,提出基于基本块的快速矩阵转置算法,从而避免对数据矩阵的列访问;提出混合旋转因子产生策略,结合查表和基于CORDIC算法在线计算方式,最大限度降低旋转因子产生的硬件开销.实验结果表明:FFT加速器原型的峰值能效为146GFLOPs/W,相比Intel Xeon CPU上的多线程FFTW实现,取得2个数量级的能效提升.
[Abstract]:Fast Fourier transform (fast Fourier transform,FFT) is the most time-consuming core algorithm in the field of digital signal processing (digital signal processing,DSP). The performance and efficiency of the algorithm will affect the execution efficiency of the whole application. Therefore, a high energy efficiency variable length FFT accelerator based on matrix transposing is designed and implemented on DSP chip. A batch and small scale FFT algorithm is developed using a variety of parallel strategies, which is parallel to instruction level and task level in large scale Cooley-Tukey FFT algorithm. A ping-pong multi-body data memory is designed to improve the computational efficiency of FFT accelerator by using the overhead between overlapping data transfer and FFT computation. Based on this memory, a fast matrix transpose algorithm based on basic block is proposed to avoid the column access to the data matrix. A hybrid rotation factor generation strategy is proposed to minimize the hardware overhead generated by the rotation factor by combining the search table with the on-line calculation method based on CORDIC algorithm. The experimental results show that the peak energy efficiency of the prototype of FFT accelerator is 146 GFLOPs / W, which is two orders of magnitude higher than that of multithreaded FFTW on Intel Xeon CPU.
【作者单位】： 国防科学技术大学计算机学院;
【基金】：国家自然科学基金项目(61402499,61502508) 湖南省自然科学基金项目(2015JJ3017)~~
【分类号】：TP332
[Abstract]:Fast Fourier transform (fast Fourier transform,FFT) is the most time-consuming core algorithm in the field of digital signal processing (digital signal processing,DSP). The performance and efficiency of the algorithm will affect the execution efficiency of the whole application. Therefore, a high energy efficiency variable length FFT accelerator based on matrix transposing is designed and implemented on DSP chip. A batch and small scale FFT algorithm is developed using a variety of parallel strategies, which is parallel to instruction level and task level in large scale Cooley-Tukey FFT algorithm. A ping-pong multi-body data memory is designed to improve the computational efficiency of FFT accelerator by using the overhead between overlapping data transfer and FFT computation. Based on this memory, a fast matrix transpose algorithm based on basic block is proposed to avoid the column access to the data matrix. A hybrid rotation factor generation strategy is proposed to minimize the hardware overhead generated by the rotation factor by combining the search table with the on-line calculation method based on CORDIC algorithm. The experimental results show that the peak energy efficiency of the prototype of FFT accelerator is 146 GFLOPs / W, which is two orders of magnitude higher than that of multithreaded FFTW on Intel Xeon CPU.
【作者单位】： 国防科学技术大学计算机学院;
【基金】：国家自然科学基金项目(61402499,61502508) 湖南省自然科学基金项目(2015JJ3017)~~
【分类号】：TP332
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