嵌入式微处理器中的低功耗Cache技术研究
发布时间：2019-01-01 13:28
【摘要】：高速缓冲存储器(Cache)作为微处理器的重要组成部分,在芯片面积和功耗上都占比过高。针对Cache功耗问题,基于分段访问Cache技术和路预测Cache技术,提出一种低功耗组相联Cache的预访问策略。在Cache中增加一个缓冲寄存器(Buffer),用以存储最近Cache命中后被访问的标签和数据子阵列信息。在开始进行标签访问之前,选中该Buffer,并将所访问的Cache标签和Buffer标签进行匹配,根据匹配结果选择采用路预测访问或分段访问方式。通过Mi Bench基准测试程序并使用Simple Scalar和Sim-Panalyzer进行实验,结果表明,与传统组相联Cache技术相比,该策略能降低25.15%的能量延迟积。
[Abstract]:Cache memory (Cache), as an important part of microprocessor, occupies a high proportion of chip area and power consumption. In order to solve the problem of Cache power consumption, a low power group associated Cache pre-access strategy is proposed based on piecewise access Cache technology and path prediction Cache technology. Add a buffer register (Buffer), to Cache to store tags and data subarray information accessed after the most recent Cache hit. Before the tag access is started, the Buffer, is selected and the visited Cache tag and the Buffer tag are matched. According to the matching results, the path prediction access or segmented access is adopted. By using Mi Bench benchmark program and using Simple Scalar and Sim-Panalyzer, the results show that compared with the conventional group associated Cache technique, this strategy can reduce the energy delay product by 25.15%.
【作者单位】： 中国电子集团公司第三十二研究所;
【分类号】：TP332
[Abstract]:Cache memory (Cache), as an important part of microprocessor, occupies a high proportion of chip area and power consumption. In order to solve the problem of Cache power consumption, a low power group associated Cache pre-access strategy is proposed based on piecewise access Cache technology and path prediction Cache technology. Add a buffer register (Buffer), to Cache to store tags and data subarray information accessed after the most recent Cache hit. Before the tag access is started, the Buffer, is selected and the visited Cache tag and the Buffer tag are matched. According to the matching results, the path prediction access or segmented access is adopted. By using Mi Bench benchmark program and using Simple Scalar and Sim-Panalyzer, the results show that compared with the conventional group associated Cache technique, this strategy can reduce the energy delay product by 25.15%.
【作者单位】： 中国电子集团公司第三十二研究所;
【分类号】：TP332
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【共引文献】
相关期刊论文 前3条
1 张丹;董雷刚;刘雅U，
本文编号：2397632
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