基于H.264视频解码器DDR2的存储器接口的设计与验证
发布时间：2019-01-03 12:33
【摘要】：H.264是国际标准化组织（ISO）和国际电信联盟（ITU）共同提出的继MPEG4之后的新一代数字视频压缩格式。作为H.264解码器的重要组成单元DDR2存储器接口，在该项目中的作用是将视频解码核产生中间数据缓存于片外存储器（或从外存中读出），同时DDR2存储器接口还提供与视频解码核的通信，视频输出控制模块通过DDR2存储接口从DDR2SDRAM中读取数据。 本论文在研究了DDR2的JEDEC标准，H.264协议的基础上，设计出了满足解码器需求的DDR2存储器接口的整体架构。根据H.264解码核的接口要求对DDR2存储器接口进行了整体架构的设计，确定系统所要实现的功能、系统的输入输出以及这些输入输出之间的关系，使其能够在整个解码器中正常良好的运行。 DDR2控制器接口由两大部分组成，分别为控制器接口和DDR2控制器。论文主要完成了整个控制器接口和DDR2控制器部分模块的RTL设计，并在文章中详细介绍了控制器接口的各个模块，以及其内部组成，，接口信号，接口时序。设计难点在于数据类型较多，仲裁情况复杂，存储方式的优化。在学习DDR2规范的基础上，研究国内外DDR2控制器的设计经验，对DDR2控制器进行系统功能分析，设计了DDR2控制器中用户接口模块，参数配置模块以及控制模块。并在此基础上详细介绍了phy模块设计方法。设计难点在于控制器中状态的转换，自刷新等操作时间的详细控制等。 在实现RTL代码设计的基础上，作者根据解码核发送的数据情况独立了搭建验证平台，进行了验证项的提取，完成了DDR2存储器接口的功能验证。难点在于解码核功能模型实现实际情况下发送数据，请求等所有的情况的全覆盖，以确保功能的健全。由于存储数据量大，所以实现数据的自动对比也是其中的难点之一。 论文设计的DDR2存储器接口主要特点是： 1.使用于H.264解码芯片，可以直接与解码核相连。 2.对发送来的数据请求进行了两级仲裁，确保请求能够正常响应，数据正常传输，提高DDR2SDRAM的存储效率。 3.支持DDR2三项新技术，充分发挥DDR2SDRAM的特性。 4.自动DDR2刷新控制，方便用户对DDR2刷新的控制。
[Abstract]:H.264 is a new digital video compression format proposed by the International Organization for Standardization (ISO) and the International Telecommunication Union (ITU) after MPEG4. As an important component of the H.264 decoder, the DDR2 memory interface is used in this project to cache the intermediate data generated by the video decoding core (or read out from the external memory). At the same time, the DDR2 memory interface also provides the communication with the video decoding core, and the video output control module reads the data from the DDR2SDRAM through the DDR2 storage interface. Based on the research of JEDEC standard and H.264 protocol of DDR2, this paper designs the whole architecture of DDR2 memory interface which meets the requirements of decoder. According to the interface requirements of H.264 decoding core, the DDR2 memory interface is designed as a whole, and the functions of the system, the input and output of the system and the relationship between these inputs and outputs are determined. Make it work well in the whole decoder. DDR2 controller interface is composed of two parts, controller interface and DDR2 controller. This paper mainly completes the RTL design of the whole controller interface and the DDR2 controller module, and introduces in detail each module of the controller interface, as well as its internal composition, interface signal, interface timing. The difficulty of design is that there are many data types, arbitration is complicated, and storage mode is optimized. Based on the study of DDR2 specification, the design experience of DDR2 controller at home and abroad is studied, and the system function of DDR2 controller is analyzed. The user interface module, parameter configuration module and control module in DDR2 controller are designed. On this basis, the design method of phy module is introduced in detail. The design difficulty lies in the conversion of the state in the controller, the detailed control of the operation time such as self-refresh, etc. Based on the design of RTL code, the author builds an independent verification platform according to the data sent by the decoding core, extracts the verification items, and completes the functional verification of the DDR2 memory interface. The difficulty lies in decoding the kernel function model to realize the full coverage of all the cases such as sending data and requesting data in practice so as to ensure the soundness of the function. Because of the large amount of data stored, automatic data comparison is one of the difficulties. The main features of the DDR2 memory interface designed in this paper are as follows: 1. Used in H. 264 decoding chip, can be directly connected to the decoding core. 2. Two levels of arbitration are carried out to ensure that the request can respond normally, the data can be transmitted normally, and the storage efficiency of DDR2SDRAM can be improved. 3. Support DDR2 three new technologies, give full play to the characteristics of DDR2SDRAM. 4. Automatic DDR2 refresh control, easy for users to DDR2 refresh control.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333;TN919.81
本文编号：2399365
[Abstract]:H.264 is a new digital video compression format proposed by the International Organization for Standardization (ISO) and the International Telecommunication Union (ITU) after MPEG4. As an important component of the H.264 decoder, the DDR2 memory interface is used in this project to cache the intermediate data generated by the video decoding core (or read out from the external memory). At the same time, the DDR2 memory interface also provides the communication with the video decoding core, and the video output control module reads the data from the DDR2SDRAM through the DDR2 storage interface. Based on the research of JEDEC standard and H.264 protocol of DDR2, this paper designs the whole architecture of DDR2 memory interface which meets the requirements of decoder. According to the interface requirements of H.264 decoding core, the DDR2 memory interface is designed as a whole, and the functions of the system, the input and output of the system and the relationship between these inputs and outputs are determined. Make it work well in the whole decoder. DDR2 controller interface is composed of two parts, controller interface and DDR2 controller. This paper mainly completes the RTL design of the whole controller interface and the DDR2 controller module, and introduces in detail each module of the controller interface, as well as its internal composition, interface signal, interface timing. The difficulty of design is that there are many data types, arbitration is complicated, and storage mode is optimized. Based on the study of DDR2 specification, the design experience of DDR2 controller at home and abroad is studied, and the system function of DDR2 controller is analyzed. The user interface module, parameter configuration module and control module in DDR2 controller are designed. On this basis, the design method of phy module is introduced in detail. The design difficulty lies in the conversion of the state in the controller, the detailed control of the operation time such as self-refresh, etc. Based on the design of RTL code, the author builds an independent verification platform according to the data sent by the decoding core, extracts the verification items, and completes the functional verification of the DDR2 memory interface. The difficulty lies in decoding the kernel function model to realize the full coverage of all the cases such as sending data and requesting data in practice so as to ensure the soundness of the function. Because of the large amount of data stored, automatic data comparison is one of the difficulties. The main features of the DDR2 memory interface designed in this paper are as follows: 1. Used in H. 264 decoding chip, can be directly connected to the decoding core. 2. Two levels of arbitration are carried out to ensure that the request can respond normally, the data can be transmitted normally, and the storage efficiency of DDR2SDRAM can be improved. 3. Support DDR2 three new technologies, give full play to the characteristics of DDR2SDRAM. 4. Automatic DDR2 refresh control, easy for users to DDR2 refresh control.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333;TN919.81
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